HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 240
HD64F7144F50V
Manufacturer Part Number
HD64F7144F50V
Description
IC SUPERH MCU FLASH 256K 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7144r
Specifications of HD64F7144F50V
Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
74
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Price
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Part Number:
HD64F7144F50V
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Part Number:
HD64F7144F50V
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10. Direct Memory Access Controller (DMAC)
Rev.4.00 Mar. 27, 2008 Page 194 of 882
REJ09B0108-0400
Figure 10.10 shows an example of timing in indirect address mode when transfer source and
indirect address storage locations are in internal memory, the transfer destination is an on-chip
peripheral module with 2-cycle access space, and transfer data is 8-bit.
Since the indirect address storage destination and the transfer source are in internal memory,
these can be accessed in one cycle. The transfer destination is 2-cycle access space, so two data
write cycles are required. One NOP cycle is required until the data read as the indirect address
is output to the address bus.
Figure 10.10 Dual Address Mode and Indirect Address Transfer Timing Example
address
address
indirect
Internal
Internal
DMAC
DMAC
buffer
buffer
data
data
bus
bus
CK
Transfer
address
source
(On-chip Memory Space to On-chip Memory Space)
read cycle
Address
Indirect
address
(1st)
NOP
Indirect
address
address
Indirect
(2nd)
cycle
NOP
NOP
read cycle
destination
Transfer
address
Transfer
(3rd)
Data
data
Data write cycle (4th)
Transfer data
Transfer data
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