HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 774

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

24. Power-Down Modes
24.3.2
Transition to Software Standby Mode: A transition is made to software standby mode if the
SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In this mode, the CPU,
on-chip peripheral functions, and the oscillator, all stop.
However, the contents of the CPU's internal registers and on-chip RAM data are retained as long
as the specified voltage is supplied. There are two types of on-chip peripheral module registers;
ones which are initialized by software standby mode, and those not initialized by that mode. For
details, refer to section 25.3, Register States in Each Operating Mode. The port high-impedance bit
(Hi-Z) in SBYCR sets the state of the I/O port either to "retained" or "high-impedance". For the
state of pins, refer to appendix A, Pin States. In software standby mode, the oscillator stops and
thus power consumption is significantly reduced.
Clearing Software Standby Mode: Software standby mode is cleared by the condition below.
• Clearing by the NMI interrupt input
• Clearing by the RES pin
Rev.4.00 Mar. 27, 2008 Page 728 of 882
REJ09B0108-0400
When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit
(NMIE) in ICR1 of the interrupt controller (INTC)) is detected, clock oscillation is started.
This clock pulse is supplied only to the watchdog timer (WDT).
After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT
before the transition to software standby mode, the WDT overflow occurs. Since this overflow
indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after
this overflow. Software standby mode is thus cleared and the NMI exception handling is
started.
When clearing software standby mode by the NMI interrupt, set CKS2 to CKS0 bits so that the
WDT overflow period will be longer than the oscillation stabilization time.
When so&tware standby mode is cleared by the falling edge of the NMI pin, the NMI pin
should be high when the CPU enters software standby mode (when the clock pulse stops) and
should be low when the CPU returns from standby mode (when the clock is initiated after the
oscillation stabilization). When software standby mode is cleared by the rising edge of the
NMI pin, the NMI pin should be low when the CPU enters software standby mode (when the
clock pulse stops) and should be high when the CPU returns from software standby mode
(when the clock is initiated after the oscillation stabilization).
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation is started, clock pulse is supplied to the entire chip. Ensure that the RES pin is held
low until clock oscillation stabilizes. When the RES pin is driven high, the CPU starts the reset
exception handling.
Software Standby Mode