HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 179

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.3.6
Table 8.5 shows the execution state for one DTC data transfer. Furthermore, table 8.6 shows the
state counts needed for execution state.
Table 8.5
N:
Table 8.6
Notes: 1. Two state access module: port, INT, CMT, SCI, etc.
The execution state count is calculated using the following formula. Σ indicates the number of
transfers by one activating source (count + 1 when CHNE bit is set to 1).
Mode
Normal
Repeat
Block transfer
Access Objective
Bus width
Access state
Execution
state
block size (default set values of DTCRB)
2. Three state access module: WDT, UBC, etc.
Execution state count = I · S
DTC Execution State Counts
Vector read
Register information
read/write
Byte data read
Word data read
Long word data read
Byte data write
Word data write
Longword data write
Internal operation
Execution State of DTC
State Counts Needed for Execution State
Vector Read I
1
1
1
Register
Information
Read/Write J
7
7
7
S
S
S
S
S
S
S
S
S
I
I
J
K
K
K
L
L
L
M
+ Σ (J · S
On-chip
RAM
32
—
1
1
1
1
1
1
1
1
J
+ K · S
Data Read K
1
1
N
On-chip
ROM
32
1
1
1
1
1
1
1
1
1
K
+ L · S
Rev.4.00 Mar. 27, 2008 Page 133 of 882
Internal I/O
Register
2*
—
—
L
2
2
4
2
2
4
) + M · S
8 or 16
8. Data Transfer Controller (DTC)
1
Data Write L
1
1
N
1
3*
—
—
3
3
6
3
3
6
M
2
8
2
4
8
2
4
8
2
4
8
External Device
REJ09B0108-0400
Internal
Operation M
1
1
1
16
2
2
4
2
2
4
2
2
4
32
2
2
2
2
2
2
2
2
2