HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 452

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13. Serial Communication Interface (SCI)
[Legend]
X: Don’t care
Rev.4.00 Mar. 27, 2008 Page 406 of 882
REJ09B0108-0400
Bit
3
2
1
0
Bit Name Initial Value R/W
MPIE
TEIE
CKE1
CKE0
0
0
0
0
R/W
R/W
R/W
R/W
Description
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
Write 0 to this bit in smart card interface mode.
When receive data including MPB = 0 is received,
receive data transfer from RSR to RDR, receive error
detection, and setting of the RDRF, FER, and ORER
flags in SSR, are not performed.
When receive data including MPB = 1 is received, the
MPB bit in SSR is set to 1, the MPIE bit is cleared to 0
automatically, and generation of RXI and ERI interrupts
(when the TIE and RIE bits in SCR are set to 1) and
FER and ORER flag setting are enabled.
Transmit End Interrupt Enable
Write 0 to this bit in smart card interface mode.
TEI cancellation can be performed by reading 1 from
the TDRE flag in SSR, then clearing it to 0 and clearing
the TEND flag to 0, or clearing the TEIE bit to 0.
Clock Enable 1 and 0
Enable or disable clock output from the SCK pin. The
clock output can be dynamically switched in GSM
mode. For details, refer to section 13.7.7, Clock Output
Control.
When the GM bit in SMR is 0:
00: Output disabled (SCK pin functions as an input pin
01: Clock output
1X: Reserved
When the GM bit in SMR is 1:
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
(ignored) or as an output pin (level is undefined))