HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 882

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

D. I/O Port Block Diagrams
Rev.4.00 Mar. 27, 2008 Page 836 of 882
REJ09B0108-0400
Pins
PD8/D8/
AUDATA0
PD9/D9/
AUDATA1
PD10/D10/
AUDATA2
PD11/D11/
AUDATA3
PDn
PD8
PD9
PD10 D10
PD11 D11
Symbol in Figure D.24
Dn
D8
(BSC)
D9
(BSC)
(BSC)
(BSC)
AUDATAm
AUDATA0
(AUD)
AUDATA1
(AUD)
AUDATA2
(AUD)
AUDATA3
(AUD)
Figure D.24 PDn/Dn/AUDATAm
F-ZTAT
version
√
√
√
√
SH7144
RES: Reset signal
PDDRL.RD: Port D data register L read signal
PDDRL.WR: Port D data register L write signal
Din: Data input timing signal
Dout: Data output timing signal
Dout
Masked ROM
version/
ROM less
version
⎯
⎯
⎯
⎯
Bus release
Software standby
AUD module standby
Available Products
Q
PDnDR
R
C
RES
PDDRL.WR
PDDRL.RD
D
Dn (BSC)
F-ZTAT
version
⎯
⎯
⎯
⎯
Din
PFC
SBYCR
AUDSYNC
AUD reset
AUDMD
Q PDnMD0
Q PDnMD1
Q PDnIOR
Q Hi-Z
AUDATAm (AUD)
AUDATAm (AUD)
SH7145
Masked ROM
version/
ROM less
version
⎯
⎯
⎯
⎯