HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 200

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9. Bus State Controller (BSC)
9.6
A strobe signal is output in external space accesses to provide primarily for SRAM or ROM direct
connections.
9.6.1
External access bus cycles are performed in 2 states. Figure 9.3 shows the basic timing of external
space access.
During a read, irrespective of operand size, all bits in the data bus width for the access space
(address) accessed by RD signal are fetched by the LSI.
During a write, the WRHH (bits 31 to 24), the WRHL (bits 23 to 16), the WRH (bits 15 to 8), and
the WRL (bits 7 to 0) signal indicate the byte location to be written.
Rev.4.00 Mar. 27, 2008 Page 154 of 882
REJ09B0108-0400
Accessing External Space
Basic Timing
Figure 9.3 Basic Timing of External Space Access
Write
Read
Address
DACK
WRxx
Data
Data
CSn
CK
RD
T1
T2