HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 367

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.7
11.7.1
MTU operation can be disabled or enabled using the module standby register. The initial setting is
for MTU operation to be halted. Register access is enabled by clearing module standby mode. For
details, refer to section 24, Power-Down Modes.
11.7.2
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The MTU will not operate properly at narrower
pulse widths.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 11.70 shows the input clock
conditions in phase counting mode.
Figure 11.70
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Notes: Phase difference and overlap
Usage Notes
Module Standby Mode Setting
Input Clock Restrictions
Pulse width
Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Overlap
Pulse width
Phase
differ-
ence
Overlap
: 1.5 states or more
: 2.5 states or more
Phase
differ-
ence
Pulse width
11.
Rev.4.00 Mar. 27, 2008 Page 321 of 882
Pulse width
Multi-Function Timer Pulse Unit (MTU)
Pulse width
REJ09B0108-0400