HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 540

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. I
Table 14.6 I
Rev.4.00 Mar. 27, 2008 Page 494 of 882
REJ09B0108-0400
S
SLA
R/W
A
DATA
P
SDA
SCL
2
C Bus Interface (IIC) Option
S
This represents the start condition. The master device changes the level on SDA
from high to low while SCL is high.
This represents the slave address. The master device sends this to select the slave
device.
This represents the direction of transmission/reception. When the R/W bit is 1, data is
transferred from the slave to the master device. When the R/W bit is 0, data is
transferred from the master to the slave device.
This represents an acknowledgement. The receiving device sends this acknowledge
bit by setting the level on SDA to low (during master transmission, the slave returns
the acknowledge bits; during master reception, the master returns the acknowledge
bits).
This represents the transfer of data. The amount of bits to be transferred in each
such operation is set by the BC2 to BC0 bits of ICMR. The MLS bit in ICMR
determines whether the data is transferred MSB first or LSB first.
This represents the stop condition. The master device changes the level on SDA
from low to high while SCL is high.
2
C Bus Data Format: Description of Symbols
SLA
1-7
R/W
8
A
9
Figure 14.5 I
1-7
DATA
2
C Bus Timing
8
9
A
1-7
DATA
8
A/A
9
P