HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 534

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14. I
Rev.4.00 Mar. 27, 2008 Page 488 of 882
REJ09B0108-0400
Bit Bit Name Initial Value R/W
2
1
AAS
ADZ
2
C Bus Interface (IIC) Option
0
0
R/(W)* Slave Address Detection Flag
R/(W)* General Call Address Detection Flag
Description
When the first frame after the start condition matches the SVA6
to SVA0 bits of SAR or when the general-call address (H'00) is
detected in the I
[Setting condition]
•
[Clearing conditions]
•
•
•
In the I
general-call address (H'00) is detected in the first frame
after the start condition.
[Setting condition]
•
[Clearing conditions]
•
•
•
When the general call address is detected while FS = 1 and
FSX = 0, the ADZ flag is set to 1 but the general call
address is not identified (the AAS flag is not set to 1).
Detection of the slave address or general call address (one
frame, including the R/W bit, is H'00) while in the slave-
receive mode and FS = 0.
Writing of data to ICDR (during transmission) or reading of
data from ICDR (during reception)
Writing of 0 to this bit after reading it as 1
Entering the master mode
Detection of the general call address (one frame,
including R/W bit, is H'00) in the slave-receive mode
(FSX = 0 or FS = 0).
Writing of data to ICDR (during transmission) or reading
of data from ICDR (during reception).
Writing 0 to this bit after reading it as 1
Entering the master mode
2
C bus format in the slave-reception mode, the
2
C bus format in the slave receive mode.