HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 218

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10. Direct Memory Access Controller (DMAC)
10.3.4
DMA channel control registers_0 to 3 (CHCR_0 to CHCR_3) are 32-bit readable/writable
registers where the operation and transmission of each channel is designated.
Rev.4.00 Mar. 27, 2008 Page 172 of 882
REJ09B0108-0400
Bit
31
to
21
20
19
18
Bit Name Initial Value R/W
⎯
DI
RO
RL
DMA Channel Control Registers_0 to 3 (CHCR_0 to CHCR_3)
All 0
0
0
0
R
(R/W)*
(R/W)*
(R/W)*
2
2
2
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Direct/Indirect
Specifies either direct address mode operation or indirect
address mode operation for channel 3 source address.
This bit is valid only in CHCR_3. For CHCR_0 to
CHCR_2, this bit is always read as 0 and the write value
should always be 0.
0: Direct access mode operation for channel 3
1: Indirect access mode operation for channel 3
Source Address Reload
Selects whether to reload the source address initial value
during channel 2 transfer. This bit is valid only for
CHCR_2. For CHCR_0, CHCR_1, and CHCR_3, this bit
is always read as 0 and the write value should always be
0.
0: Does not reload source address
1: Reloads source address
Request Check Level
Selects whether to output DRAK notifying external device
of DREQ received, with active high or active low. This bit
is valid only for CHCR_0 and CHCR_1. For CHCR_2 and
CHCR_3, this bit is always read as 0 and the write value
should always be 0.
0: Output DRAK with active high
1: Output DRAK with active low