HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 36

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 I/O Ports
Figure 18.1 Port A (SH7144)...................................................................................................... 634
Figure 18.2 Port A (SH7145)...................................................................................................... 635
Figure 18.3 Port B....................................................................................................................... 639
Figure 18.4 Port C....................................................................................................................... 642
Figure 18.5 Port D (SH7144)...................................................................................................... 645
Figure 18.6 Port D (SH7145)...................................................................................................... 646
Figure 18.7 Port E (SH7144) ...................................................................................................... 650
Figure 18.8 Port E (SH7145) ...................................................................................................... 651
Figure 18.9 Port F ....................................................................................................................... 654
Section 19 Flash Memory (F-ZTAT Version)
Figure 19.1 Block Diagram of Flash Memory............................................................................ 658
Figure 19.2 Flash Memory State Transitions.............................................................................. 659
Figure 19.3 Boot Mode............................................................................................................... 661
Figure 19.4 User Program Mode ................................................................................................ 662
Figure 19.5 Flash Memory Block Configuration........................................................................ 663
Figure 19.6 Programming/Erasing Flowchart Example in User Program Mode ........................ 673
Figure 19.7 Flowchart for Flash Memory Emulation in RAM ................................................... 674
Figure 19.8 Example of RAM Overlap Operation (RAM[2:0] = B'000).................................... 675
Figure 19.9 Program/Program-Verify Flowchart........................................................................ 677
Figure 19.10 Erase/Erase-Verify Flowchart ............................................................................... 679
Figure 19.11 Power On/Off Timing (Boot Mode)...................................................................... 685
Figure 19.12 Power On/Off Timing (User Program Mode)........................................................ 686
Figure 19.13 Mode Transit Timing
(Example: Boot Mode → User Mode ⇔ User Program Mode) ............................ 687
Section 20 Mask ROM
Figure 20.1 Mask ROM Block Diagram..................................................................................... 689
Section 22 User Debugging Interface (H-UDI)
Figure 22.1 H-UDI Block Diagram ............................................................................................ 694
Figure 22.2 Data Input/Output Timing Chart (1)........................................................................ 701
Figure 22.3 Data Input/Output Timing Chart (2)........................................................................ 702
Figure 22.4 Data Input/Output Timing Chart (3)........................................................................ 702
Figure 22.5 Serial Data Input/Output.......................................................................................... 704
Section 23 Advanced User Debugger (AUD)
Figure 23.1 AUD Block Diagram............................................................................................... 706
Figure 23.2 Example of Data Output (32-Bit Output) ................................................................ 711
Figure 23.3 Example of Output in Case of Successive Branches ............................................... 711
Figure 23.4 AUDATA Input Format .......................................................................................... 712
Rev.4.00 Mar. 27, 2008 Page xxxiv of xliv
REJ09B0108-0400