HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 527

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note:
Bit
1
Bit Name Initial Value R/W
IRIC
*
Only 0 can be written to clear the flag.
0
R/(W)* •
Description
•
•
[Clearing conditions]
•
•
(This may not be a clearing condition. For details, see the
following operation description on DTC.)
I
When a slave address (SVA or SVAX) matches (i.e.,
when the AAS or AASX flag is set to 1), and at the
end of data transfer up to the subsequent
retransmission start condition or stop condition
detection (i.e., at the rising edge of the 9th cycle of
transmission or receive clock)
When the general call address has been detected
(i.e., when 0 is received for R/W and the ADZ flag is
set to 1) and at the end of data reception up to the
subsequent retransmission start condition or stop
condition detection (i.e., at the rising edge of the 9th
cycle of receive clock)
When the ACKE bit is 1, and 1 is received as an
acknowledge bit
(i.e., when the ACKB bit is set to 1)
When the stop condition is detected while the
STOPIM bit is 0
(i.e., when the STOP or the ESTP flag is set to 1)
Synchronous serial format
When the transfer of data has been completed
(i.e., at the rising edge of the 8th transmit/receive
clock)
When a start condition is detected with serial format
When a condition occurs in which the ICDRE or
ICDRF flag is set to 1 in any operating mode.
When a start condition is detected in transmit mode
(i.e., when a start condition is detected and the
ICDRE flag is set to 1 in transmit mode)
When transmitting the data in the ICDR register buffer
(i.e., when data is transferred from ICDRT to ICDDRS
in transmit mode and the ICDRE flag is set to 1, or
data is transferred from ICDRS to ICDRR in receive
mode and the ICDRF flag is set to 1.)
When 0 is written in IRIC after reading IRIC = 1
When ICDR is read or written to by DTC
2
C bus format in the slave mode
Rev.4.00 Mar. 27, 2008 Page 481 of 882
14. I
2
C Bus Interface (IIC) Option
REJ09B0108-0400