HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 219

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
17
16
15
14
Bit Name
AM
AL
DM1
DM0
Initial Value
0
0
0
0
R/W
(R/W)*
(R/W)*
R/W
R/W
2
2
Description
Acknowledge Mode
In dual address mode, selects whether to output
DACK in the data write cycle or data read cycle. In
single address mode, DACK is always output
irrespective of the setting of this bit. This bit is valid
only for CHCR_0 and CHCR_1. For CHCR_2 and
CHCR_3, this bit is always read as 0 and the write
value should always be 0.
0: Outputs DACK during read cycle
1: Outputs DACK during write cycle
Acknowledge Level
Specifies whether to set DACK (acknowledge) signal
output to active high or active low. This bit is valid
only with CHCR_0 and CHCR_1. For CHCR_2 and
CHCR_3, this bit is always read as 0 and the write
value should always be 0.
0: Active high output
1: Active low output
Destination Address Mode 1, 0
These bits specify increment/decrement of the DMA
transfer destination address. These bit specifications
are ignored when transferring data from an external
device to address space in single address mode.
00: Destination address fixed
01: Destination address incremented (+1 during 8-bit
10: Destination address decremented (–1 during 8-bit
11: Setting prohibited
transfer, +2 during 16-bit transfer, +4 during 32-
bit transfer)
transfer, –2 during 16-bit transfer, –4 during 32-bit
transfer)
10. Direct Memory Access Controller (DMAC)
Rev.4.00 Mar. 27, 2008 Page 173 of 882
REJ09B0108-0400