LPC2925FBD100,551 NXP Semiconductors, LPC2925FBD100,551 Datasheet
LPC2925FBD100,551
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LPC2921/2923/2925 ARM9 microcontroller with CAN, LIN, and USB Rev. 03 — 14 April 2010 1. General description The LPC2921/2923/2925 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies 125 MHz, Full-speed USB 2.0 ...
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... NXP Semiconductors Other peripherals: Two 10-bit ADCs, 8-channels each, with 3.3 V measurement range provide 8 analog inputs each with conversion times as low as 2.44 μs per channel. Each channel provides a compare function to minimize interrupts. Multiple trigger-start option for all ADCs: timer, PWM, other ADC and external signal input ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Name Description plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm LPC2921FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm LPC2923FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm LPC2925FBD100 LQFP100 3 ...
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... NXP Semiconductors 4. Block diagram LPC2921/2923/2925 VECTORED INTERRUPT CONTROLLER CLOCK GENERATION UNIT RESET GENERATION UNIT POWER MANAGEMENT UNIT TIMER0/1 MTMR PWM0/1/2/3 3.3 V ADC1/2 QUADRATURE ENCODER CAN0/1 GLOBAL ACCEPTANCE FILTER UART/LIN0 C0/1 Grey-shaded blocks represent peripherals and memory regions accessible by the GPDMA. Fig 1. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description 5.2.1 General description The LPC2921/2923/2925 uses three ports: port 1 with 32 pins, port 1 with 28 pins, and port 5 with 2 pins. Ports 4/3/2 are not used. The pin to which each function is assigned is controlled by the SFSP registers in the SCU. The functions combined on each port pin are shown in the pin description tables in this section ...
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... NXP Semiconductors Table 3. LQFP100 pin assignment Pin name Pin [2] P5[19]/USB_D+ 12 [2] P5[18]/USB_D− DD(IO DD(CORE SS(CORE SS(IO) [1] P1[27]/CAP1[2]/ 18 TRAP2/PMAT3[3] [1] P1[26]/PMAT2[0]/ 19 TRAP3/PMAT3[ DD(IO) [1] P1[25]/PMAT1[0]/ 21 USB_VBUS/ PMAT3[1] [1] P1[24]/PMAT0[0]/ 22 USB_CONNECT/ PMAT3[0] [1] P1[23]/RXD0 23 [1] P1[22]/TXD0/ 24 USB_UP_LED [1] TMS ...
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... NXP Semiconductors Table 3. LQFP100 pin assignment Pin name Pin [1] P1[10]/SDI1/SDA0 SS(CORE DD(CORE) [1] P1[9]/SDO1 SS(IO) [1] P1[8]/SCS1[0]/ 45 TXDL1/CS0 [1] P1[7]/SCS1[3]/RXD1 46 [1] P1[6]/SCS1[2]/TXD1 47 [1] P1[5]/SCS1[1]/ 48 PMAT3[5] [1] P1[4]/SCS2[2]/ 49 PMAT3[4] [1] TRST 50 [1] RST SS(OSC) [3] XOUT_OSC 53 [3] XIN_OSC DD(OSC_PLL) ...
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... NXP Semiconductors Table 3. LQFP100 pin assignment Pin name Pin V 74 DDA(ADC3V3) [1] JTAGSEL 75 n.c. 76 [3] VREFP 77 [3] VREFN 78 [4] P0[8]/IN1[0] 79 [4] P0[9]/IN1[1] 80 [4] P0[10]/IN1[2]/ 81 PMAT1[0] [4] P0[11]/IN1[3]/ 82 PMAT1[ SS(IO) [4] P0[12]/IN1[4]/ 84 PMAT1[2] [4] P0[13]/IN1[5]/ 85 PMAT1[3] [4] P0[14]/IN1[6]/ 86 PMAT1[4] [4] P0[15]/IN1[7]/ ...
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... NXP Semiconductors Table 3. LQFP100 pin assignment Pin name Pin [4] P0[23]/IN2[7]/ 99 PMAT2[5]/A19 [1] TDI 100 [1] Bidirectional pad; analog port; plain input; 3-state output; slew rate control tolerant; TTL with hysteresis; programmable pull-up/pull-down/repeater. [2] USB pad. [3] Analog pad; analog I/O. [4] Analog I/O pad. ...
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... NXP Semiconductors • Write buffers for the AHB and TCM buses. Enhanced 16 × 32 multiplier capable of single-cycle MAC operations and 16-bit fixed- • point DSP instructions to accelerate signal-processing algorithms and applications. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously ...
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Memory map LPC2921/2923/2925 0xFFFF FFFF VIC 0xFFFF F000 PCR/VIC reserved 0xFFFF C000 subsystem CGU1 0xFFFF B000 PMU 0xFFFF A000 RGU 0xFFFF 9000 CGU0 0xFFFF 8000 0xE00E 0000 reserved 0xE00C A000 quadrature encoder 0xE00C 9000 PWM3 0xE00C 8000 PWM2 0xE00C ...
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... NXP Semiconductors 6.6 Reset, debug, test, and power description 6.6.1 Reset and power-up behavior The LPC2921/2923/2925 contains external reset input and internal power-up reset circuits. This ensures that a reset is extended internally until the oscillators and flash have reached a stable state. See ...
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... NXP Semiconductors 6.6.3.1 ETM/ETB The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace buffer. A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured in a format that a user can easily understand. The ETB stores trace data produced by the ETM ...
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... NXP Semiconductors Two of the base clocks generated by the CGU0 are used as input into a second, dedicated CGU (CGU1). The CGU1 uses its own PLL and fractional dividers to generate the base clock for the USB controller and one base clock for an independent clock output. ...
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... NXP Semiconductors found in the specific subsystem description. Some branch clocks have special protection since they clock vital system parts of the device and should not be switched off. See Section 6.15.5 Table 7. Base clock BASE_SAFE_CLK BASE_SYS_CLK BASE_PCR_CLK BASE_IVNSS_CLK LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB for more details of how to control the individual branch clocks ...
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... NXP Semiconductors Table 7. Base clock BASE_MSCSS_CLK BASE_UART_CLK BASE_ICLK0_CLK BASE_SPI_CLK BASE_TMR_CLK BASE_ADC_CLK reserved BASE_ICLK1_CLK [1] This clock is always on (cannot be switched off for system safety reasons) [2] In the peripheral subsystem parts of the timers, watchdog timer, SPI and UART have their own clock source. See [3] The clock should remain activated when system wake-up on timer or UART is required ...
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... NXP Semiconductors 6.8 Flash memory controller The flash memory has a 128-bit wide data interface and the flash controller offers two 128-bit buffer lines to improve system performance. The flash has to be programmed initially via JTAG. In-system programming must be supported by the bootloader. Flash memory contents can be protected by disabling JTAG access ...
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... NXP Semiconductors With dual buffering, a secondary buffer line is used, the output of the flash being considered as the primary buffer primary buffer, hit data can be copied to the secondary buffer line, which allows the flash to start a speculative read of the next flash word. Both buffer lines are invalidated after: • ...
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... NXP Semiconductors Table 10. Flash memory sector number The index sector is a special sector in which the JTAG access protection and sector security are located. The address space becomes visible by setting the FS_ISS bit and overlaps the regular flash sector’s address space. ...
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... NXP Semiconductors 6.8.6 EEPROM EEPROM is a non-volatile memory mostly used for storing relatively small amounts of data, for example for storing settings. It contains one 16 kB memory block and is byte-programmable and byte-erasable. The EEPROM can be accessed only through the flash controller. 6.9 General Purpose DMA (GPDMA) controller The GPDMA controller allows peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions ...
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... NXP Semiconductors The USB device controller has the following features: • Fully compliant with USB 2.0 specification (full speed). • Supports 32 physical (16 logical) endpoints with endpoint buffer RAM. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Scalable realization of endpoints at run time. ...
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... NXP Semiconductors 6.11 General subsystem 6.11.1 General subsystem clock description The general subsystem is clocked by CLK_SYS_GESS, see 6.11.2 Chip and feature identification The Chip/Feature ID (CFID) module contains registers which show and control the functionality of the chip. It contains identify the silicon and also registers containing information about the features enabled or disabled on the chip ...
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... NXP Semiconductors 6.11.4.1 Pin description The event router module in the LPC2921/2923/2925 is connected to the pins listed below. The pins are combined with other functions on the port pins of the LPC2921/2923/2925. Table 12 Table 12. Symbol EXTINT[0:3] CAN0 RXD CAN1 RXD I2C0_SCL I2C1_SCL LIN0 RXD LIN1 RXD ...
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... NXP Semiconductors • Watchdog control register change-protected with key • Programmable 32-bit watchdog timer period with programmable 32-bit prescaler. 6.12.2.1 Functional description The watchdog timer consists of a 32-bit counter with a 32-bit prescaler. The watchdog should be programmed with a time-out value and then periodically restarted ...
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... NXP Semiconductors – Set HIGH on match. – Toggle on match. – Do nothing on match. • Pause input pin (MSCSS timers only). The timers are designed to count cycles of the clock and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. They also include capture inputs to trap the timer value when an input signal changes state, optionally generating an interrupt ...
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... NXP Semiconductors • Register locations conform to 550 industry standard. • Receiver FIFO trigger points at 1 byte, 4 bytes, 8 bytes and 14 bytes. • Built-in baud rate generator. • Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. ...
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... NXP Semiconductors • Internal loopback test mode. The SPI module can operate in: • Master mode: – Normal transmission mode – Sequential slave mode • Slave mode 6.12.5.1 Functional description The SPI module is a master or slave interface for synchronous serial communication with peripheral devices that have either Motorola SPI or Texas Instruments Synchronous Serial Interfaces ...
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... NXP Semiconductors 6.12.5.3 Clock description The SPI modules are clocked by two different clocks; CLK_SYS_PESS and CLK_SPIx ( 2), see power management. The frequency of all clocks CLK_SPIx is identical as they are derived from the same base clock BASE_CLK_SPI. The register interface towards the system bus is clocked by CLK_SYS_PESS ...
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... NXP Semiconductors 6.12.6.3 Clock description The GPIO modules are clocked by several clocks, all of which are derived from BASE_SYS_CLK; CLK_SYS_PESS and CLK_SYS_GPIOx ( 5), see Section power management. The frequency of all clocks CLK_SYS_GPIOx is identical to CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK. ...
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... NXP Semiconductors 6.13.2 LIN The LPC2921/2923/2925 contain two LIN 2.0 master controllers. These can be used as dedicated LIN 2.0 master controllers with additional support for sync break generation and with hardware implementation of the LIN protocol according to spec 2.0. The key features are: • ...
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... NXP Semiconductors • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • ...
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... NXP Semiconductors The PWMs can be used to generate waveforms in which the frequency, duty cycle and rising and falling edges can be controlled very precisely. Capture inputs are provided to measure event phases compared to the main counter. Depending on the applications, these inputs can be connected to digital sensor motor outputs or digital external signals. ...
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... NXP Semiconductors capture capture PAUSE Fig 5. Modulation and Sampling Control SubSystem (MSCSS) block diagram 6.14.2 Pin description The pins of the LPC2921/2923/2925 MSCSS associated with the two ADC modules are described in Section Section Section LPC2921_23_25_3 Product data sheet AHB-TO-APB BRIDGE MSCSS QEI ...
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... NXP Semiconductors Remark: The IDX0 function for the QEI, the external start function for ADC1, and the TRAP0/1 functions for the PWM0/1 are not pinned out on the LPC2921/2923/2925. 6.14.3 Clock description The MSCSS is clocked from a number of different sources: • CLK_SYS_MSCSS_A clocks the AHB side of the AHB-to-APB bus bridge • ...
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... NXP Semiconductors A mechanism is provided to modify configuration of the ADC and control the moment at which the updated configuration is transferred to the ADC domain. The ADC clock is limited to 4.5 MHz maximum frequency and should always be lower than or equal to the system clock frequency. To meet this constraint or to select the desired lower sampling frequency, the clock generation unit provides a programmable fractional system-clock divider dedicated to the ADC clock ...
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... NXP Semiconductors 6.14.4.3 Clock description The ADC modules are clocked from two different sources; CLK_MSCSS_ADCx_APB and CLK_ADCx ( 2), see and CLK_MSCSS_ADCx_APB branch clocks for power management ADC is unused both its CLK_MSCSS_ADCx_APB and CLK_ADCx can be switched off. The frequency of all the CLK_MSCSS_ADCx_APB clocks is identical to CLK_MSCSS_APB since they are derived from the same base clock BASE_MSCSS_CLK ...
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... NXP Semiconductors • Motor controller: The PWM provides multi-phase outputs, and these outputs can be controlled to have a certain pattern sequence. In this way the force/torque of the motor can be adjusted as desired. This makes the PWM function as a motor drive. APB system bus IRQ pwm IRQ capt_match Fig 7 ...
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... NXP Semiconductors 6.14.5.3 Master and slave mode A PWM module can provide synchronization signals to other modules (also called Master mode). The signal sync_out is a pulse of one clock cycle generated when the internal PWM counter (re)starts. The signal trans_enable_out is a pulse synchronous to sync_out, generated if a transfer from system registers to PWM shadow registers occurred when the PWM counter restarted ...
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... NXP Semiconductors 6.14.6.1 Pin description MSCSS timer 0 has no external pins. MSCSS timer 1 has a PAUSE pin available as external pin. The PAUSE pin is combined with other functions on the port pins of the LPC2921/2923/2925. MSCSS timer 1 external pin. Table 22. Symbol MSCSS PAUSE 6.14.6.2 Clock description ...
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... NXP Semiconductors 6.14.7.1 Pin description The QEI module in the MSCSS has the following pins. These are combined with other functions on the port pins of the LPC2921/2923/2925. Table 23. Symbol QEI0 PHA QEI0 PHB Remark: The index function for the QEI is not pinned out on the LPC2921/2923/2925. ...
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... NXP Semiconductors EXTERNAL OSCILLATOR LOW POWER RING OSCILLATOR CGU0 REGISTERS AHB2DTL BRIDGE RGU REGISTERS POR reset from watchdog counter RST (device pin) Fig 8. Power, Clock, and Reset control SubSystem (PCRSS) block diagram 6.15.1 Clock description The PCRSS is clocked by a number of different clocks. CLK_SYS_PCRSS clocks the ...
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... NXP Semiconductors 6.15.2 Clock Generation Unit (CGU0) The key features are: • Generation of 11 base clocks selectable from several embedded clock sources. • Crystal oscillator with power-down. • Control PLL with power-down. • Very low-power ring oscillator, always on to provide a safe clock. ...
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... NXP Semiconductors CLOCK GENERATION UNIT (CGU0) 400 kHz LP_OSC EXTERNAL PLL OSCILLATOR FREQUENCY MONITOR Fig 9. Block diagram of the CGU0 (see There are two primary clock generators: a low-power ring oscillator (LP_OSC) and a crystal oscillator. See LP_OSC is the source for the BASE_PCR_CLK that clocks the CGU itself and for BASE_SAFE_CLK that clocks a minimum of other logic in the device (like the watchdog timer) ...
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... NXP Semiconductors Configuration of the CGU0: choice can be made from the primary and secondary clock generators according to Figure 10. Fig 10. Structure of the clock generation scheme Any output generator (except for BASE_SAFE_CLK and BASE_PCR_CLK) can be connected to either a fractional divider (FDIV[0:6 one of the outputs of the PLL or to LP_OSC/crystal oscillator directly ...
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... NXP Semiconductors generator. The RDET register keeps track of which clocks are active and inactive, and the appropriate ‘CLK_SEL’ values are masked and unmasked accordingly. Each clock detector can also generate interrupts at clock activation and deactivation so that the system can be notified of a change in internal clock status. ...
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... NXP Semiconductors input clock CCO Fig 11. PLL block diagram Triple output phases: clock outputs can be enabled by setting register P23EN to logic 1, thus giving three clocks with a 120° phase difference. In this mode all three clocks generated by the analog section are sent to the output dividers. When the PLL has not yet achieved lock the second and third phase output dividers run unsynchronized, which means that the phase relation of the output clocks is unknown ...
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... NXP Semiconductors 6.15.3 Clock generation for USB (CGU1) The CGU1 block is functionally identical to the CGU0 block and generates the clock for the USB interface and a dedicated output clock. The CGU1 block uses its own PLL and fractional divider. The PLLs used in CGU0 and CGU1 are identical (see The clock input to the CGU1 PLL is provided by one of two base clocks generated in the CGU0: BASE_ICLK0_CLK or BASE_ICLK1_CLK ...
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... NXP Semiconductors • Register write-protection mechanism to prevent unintentional resets 6.15.4.1 Functional description Each reset output is defined as a combination of reset input sources including the external reset input pins and internal power-on reset, see this table form a sort of cascade to provide the multiple levels of impact that a reset may have ...
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... NXP Semiconductors Table 28. Symbol RST 6.15.5 Power Management Unit (PMU) This module enables software to actively control the system’s power consumption by disabling clocks not required in a particular operating mode. Using the base clocks from the CGU as input, the PMU generates branch clocks to the rest of the LPC2921/2923/2925 ...
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... NXP Semiconductors Table 29. Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’ Indicates that the related register bit is readable and writable ...
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... NXP Semiconductors Table 29. Legend: ‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored ‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored ‘+’ Indicates that the related register bit is readable and writable ...
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... NXP Semiconductors Interrupt-request masking is performed individually per interrupt target by comparing the priority level assigned to a specific interrupt request with a target-specific priority threshold. The priority levels are defined as follows: • Priority level 0 corresponds to ‘masked’ (i.e. interrupt requests with priority 0 never lead to an interrupt). ...
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... NXP Semiconductors 7. Limiting values Table 30. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Supply pins P total power dissipation tot V core supply voltage DD(CORE) V oscillator and PLL supply DD(OSC_PLL) voltage V 3.3 V ADC analog supply DDA(ADC3V3) voltage V input/output supply voltage ...
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... NXP Semiconductors Table 30. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter ESD V electrostatic discharge ESD voltage [1] Based on package heat transfer, not device power consumption. [2] Peak current must be limited at 25 times average current. [3] For I/O Port 0, the maximum input voltage is defined by V ...
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... NXP Semiconductors 8. Static characteristics Table 31. Static characteristics DD(CORE) DD(OSC_PLL) DD(IO) measured with respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter Supplies Core supply V core supply voltage DD(CORE) I core supply current DD(CORE) I/O supply V input/output supply DD(IO) voltage ...
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... NXP Semiconductors Table 31. Static characteristics DD(CORE) DD(OSC_PLL) DD(IO) measured with respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter I HIGH-level input leakage LIH current I LOW-level input leakage LIL current I pull-down input current I(pd) I pull-up input current I(pu) C input capacitance ...
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... NXP Semiconductors Table 31. Static characteristics DD(CORE) DD(OSC_PLL) DD(IO) measured with respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter I LOW-level short-circuit OLS output current Oscillator V voltage on pin XIN_OSC XIN_OSC R crystal series resistance s(xtal) C input capacitance i Power-up reset V high trip level voltage ...
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... NXP Semiconductors Table 32. ADC static characteristics DDA(ADC3V3) amb Symbol Parameter V voltage on pin VREFN VREFN V voltage on pin VREFP VREFP V analog input voltage IA Z input impedance i C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 14. ADC characteristics LPC2921_23_25_3 Product data sheet ...
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... NXP Semiconductors 8.1 Power consumption I DD(CORE) (mA) Fig 15 DD(CORE) (mA) Fig 16. I LPC2921_23_25_3 Product data sheet °C; active mode entered executing code from flash; core voltage 1.8 V; all Conditions: T amb peripherals enabled but not configured to run. at different core frequencies (active mode) DD(CORE) 80 125 MHz ...
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... NXP Semiconductors I DD(CORE) (mA) Fig 17. 8.2 Electrical pin characteristics V (mV) Fig 18. Typical LOW-level output voltage versus LOW-level output current LPC2921_23_25_3 Product data sheet 80 125 MHz 60 100 MHz 80 MHz 40 40 MHz 20 10 MHz 0 −40 −15 10 Conditions: active mode entered executing code from flash; core voltage 1.8 V; all peripherals enabled but not configured to run ...
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... NXP Semiconductors V Fig 19. Typical HIGH-level output voltage versus HIGH-level output current I (μA) Fig 20. Typical pull-down current versus temperature LPC2921_23_25_3 Product data sheet 3.5 OH (V) 3.0 2.5 2.0 1.0 2 3.3 V. DD(IO) 80 I(pd −40 − 3 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors I (μA) Fig 21. Typical pull-up current versus temperature LPC2921_23_25_3 Product data sheet −20 I(pu) −40 −60 −80 −100 −40 − All information provided in this document is subject to legal disclaimers. Rev. 03 — 14 April 2010 LPC2921/2923/2925 ARM9 microcontroller with CAN, LIN, and USB ...
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... NXP Semiconductors 9. Dynamic characteristics 9.1 Dynamic characteristics: I/O and CLK_OUT pins, internal clock, oscillators, PLL, and CAN Table 33. Dynamic characteristics DD(CORE) DD(OSC_PLL) DD(IO) ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter I/O pins t HIGH to LOW THL transition time ...
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... NXP Semiconductors f ref(RO) (kHz) Fig 22. Low-power ring oscillator thermal characteristics LPC2921_23_25_3 Product data sheet 520 510 500 490 480 −40 −15 10 All information provided in this document is subject to legal disclaimers. Rev. 03 — 14 April 2010 LPC2921/2923/2925 ARM9 microcontroller with CAN, LIN, and USB 1 ...
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... NXP Semiconductors 9.2 USB interface Table 34. Dynamic characteristics: USB pins (full-speed) Ω pF 1 Symbol Parameter t rise time r t fall time f t differential rise and fall time FRFM matching V output signal crossover voltage CRS t source SE0 interval of EOP FEOPT t source jitter for differential transition ...
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... NXP Semiconductors 9.3 Dynamic characteristics: I Table 35. Dynamic characteristic DD(CORE) DD(OSC_PLL) DD(IO) ground; positive currents flow into the IC; unless otherwise specified Symbol Parameter t output fall time f(o) [1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T temperature on wafer level. Cased products are tested at T test conditions to cover the specified temperature and power supply voltage range. Typical ratings are not guaranteed. The values listed are at room temperature (25 ° ...
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... NXP Semiconductors 9.4 Dynamic characteristics: SPI Table 36. Dynamic characteristics of SPI pins DD(CORE) DD(OSC_PLL) DD(IO) measured with respect to ground; positive currents flow into the IC; unless otherwise specified. Symbol Parameter f SPI operating frequency SPI t SPI_MISO set-up time su(SPI_MISO) [1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T temperature on wafer level ...
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... NXP Semiconductors 9.5 Dynamic characteristics: flash memory and EEPROM Table 37. − amb V DDA(ADC3V3) Symbol N endu t ret t prog init t wr(pg) t fl(BIST) t a(clk) t a(A) [1] Number of program/erase cycles. Table 38. − amb V DDA(ADC3V3) Symbol f clk N endu t ret LPC2921_23_25_3 Product data sheet Flash characteristics ° ° ...
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... NXP Semiconductors 9.6 Dynamic characteristics: ADC1/2 Table 39. ADC dynamic characteristics DD(CORE) DD(OSC_PLL) DD(IO) [1] ground. Symbol Parameter f ADC input frequency i(ADC) f maximum sampling rate s(max) t conversion time conv [1] All parameters are guaranteed over the virtual junction temperature range by design. Pre-testing is performed at T temperature on wafer level. Cased products are tested at T test conditions to cover the specified temperature and power supply voltage range ...
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... NXP Semiconductors core frequency (MHz) Fig 26. Core operating frequency versus core voltage for different temperatures 10.2 Suggested USB interface solutions LPC29xx Fig 27. LPC2921/2923/2925 USB interface on a self-powered device LPC2921_23_25_3 Product data sheet 145 135 25 °C 45 °C 65 °C 85 °C 125 115 105 1 ...
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... NXP Semiconductors LPC29xx Fig 28. LPC2921/2923/2925 USB interface on a bus-powered device 10.3 SPI signal forms SCKn (CPOL = 0) SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 29. SPI timing in master mode LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB V DD(IO USB_UP_LED 1.5 kΩ USB_VBUS Ω ...
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... NXP Semiconductors SCKn (CPOL = 0) SCKn (CPOL = 1) CPHA = 1 CPHA = 0 Fig 30. SPI timing in slave mode LPC2921_23_25_3 Product data sheet ARM9 microcontroller with CAN, LIN, and USB SDIn MSB IN SDOn MSB OUT SDIn MSB IN DATA VALID SDOn MSB OUT DATA VALID All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 10.4 XIN_OSC input The input voltage to the on-chip oscillators is limited to 1 the oscillator is driven by a clock in slave mode recommended that the input be coupled through a capacitor with C = 100 pF. To limit the input voltage to the specified range, choose an additional i capacitor to ground C mode, a minimum of 200 mV (RMS) is needed ...
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... NXP Semiconductors 11. Package outline LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 33. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. LPC2921_23_25_3 Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers ...
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... NXP Semiconductors 13. Abbreviations Table 42. Abbreviation AF AHB AMBA APB CCO CISC DMA DSP DTL EOP ETB ETM FIQ GPDMA GPIO IRQ LIN LUT MAC MSC PHY PLL Q-SPI RISC SCU SFSP TTL UART USB 14. References [1] UM10316 — LPC29xx user manual [2] ARM — ARM web site [3] ARM-SSP — ...
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... NXP Semiconductors 15. Revision history Table 43. Revision history Document ID LPC2921_23_25_3 Modifications: LPC2921_23_25_2 LPC2921_23_25_1 LPC2921_23_25_3 Product data sheet Release date Data sheet status 20100414 Product data sheet • Section 1: Target market “medical” removed. • Document template updated. • USB logo added. 20091208 ...
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... Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2.1 General description . . . . . . . . . . . . . . . . . . . . . 5 5.2.2 LQFP100 pin assignment . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . . 9 6.1 Architectural overview . . . . . . . . . . . . . . . . . . . 9 6.2 ARM968E-S processor . . . . . . . . . . . . . . . . . . . 9 6 ...
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... NXP Semiconductors 6.15 Power, Clock, and Reset control SubSystem (PCRSS 6.15.1 Clock description . . . . . . . . . . . . . . . . . . . . . . 41 6.15.2 Clock Generation Unit (CGU0 6.15.2.1 Functional description 6.15.2.2 PLL functional description . . . . . . . . . . . . . . . 45 6.15.2.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 46 6.15.3 Clock generation for USB (CGU1 6.15.3.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 47 6.15.4 Reset Generation Unit (RGU ...