LPC2925FBD100,551 NXP Semiconductors, LPC2925FBD100,551 Datasheet - Page 37

• Manufacturer Part Number: LPC2925FBD100,551
• Description: IC ARM9 MCU FLASH 512KB 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2900r

Specifications of LPC2925FBD100,551

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 125MHz
• Connectivity: CAN, I²C, LIN, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16K x 8
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 16x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC29
• Core: ARM968E-S
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935287116551

NXP Semiconductors
LPC2921_23_25_3
Product data sheet
Fig 7.
APB system bus
IRQ capt_match
PWM block diagram
6.14.5.2 Synchronizing the PWM counters
IRQ pwm
The PWM block diagram in
functionality is split into two major parts, a APB domain and a PWM domain, both of which
run on clocks derived from the BASE_MSCSS_CLK. This split into two domains affects
behavior from a system-level perspective. The actual PWM and prescale counters are
located in the PWM domain but system control takes place in the APB domain.
The actual PWM consists of two counters; a 16-bit prescale counter and a 16-bit PWM
counter. The position of the rising and falling edges of the PWM outputs can be
programmed individually. The prescale counter allows high system bus frequencies to be
scaled down to lower PWM periods. Registers are available to capture the PWM counter
values on external events.
Note that in the Modulation and Sampling Control SubSystem (MSCSS), each PWM has
its individual clock source CLK_MSCSS_PWMx (x runs from 0 to 3). Both the prescale
and the timer counters within each PWM run on this clock CLK_MSCSS_PWMx, and all
time references are related to the period of this clock. See
generation of these clocks.
A mechanism is included to synchronize the PWM period to other PWMs by providing a
sync input and a sync output with programmable delay. Several PWMs can be
synchronized using the trans_enable_in/trans_enable_out and sync_in/sync_out ports.
See
LPC2921/2923/2925. PWM0 can be master over PWM1; PWM1 can be master over
PWM2, etc.
•
Motor controller: The PWM provides multi-phase outputs, and these outputs can be
controlled to have a certain pattern sequence. In this way the force/torque of the
motor can be adjusted as desired. This makes the PWM function as a motor drive.
Figure 5
REGISTERS
CONTROL
PWM
&
for details of the connections of the PWM modules within the MSCSS in the
All information provided in this document is subject to legal disclaimers.
PWM counter value
Rev. 03 — 14 April 2010
capture data
config data
APB DOMAIN
update
Figure 7
IRQs
shows the basic architecture of each PWM. PWM
ARM9 microcontroller with CAN, LIN, and USB
PWM DOMAIN
LPC2921/2923/2925
sync_in
sync_out
REGISTERS
PRESCALE
COUNTER,
COUNTER
SHADOW
PWM,
transfer_enable_in
transfer_enable_out
&
Section 6.15
© NXP B.V. 2010. All rights reserved.
for information on
match outputs
capture inputs
trap input
carrier inputs
002aad837
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