LPC2925FBD100,551 NXP Semiconductors, LPC2925FBD100,551 Datasheet - Page 38

• Manufacturer Part Number: LPC2925FBD100,551
• Description: IC ARM9 MCU FLASH 512KB 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2900r

Specifications of LPC2925FBD100,551

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 125MHz
• Connectivity: CAN, I²C, LIN, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16K x 8
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 16x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC29
• Core: ARM968E-S
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935287116551

NXP Semiconductors
LPC2921_23_25_3
Product data sheet
6.14.5.3 Master and slave mode
6.14.5.4 Pin description
6.14.5.5 Clock description
6.14.6 Timers in the MSCSS
A PWM module can provide synchronization signals to other modules (also called Master
mode). The signal sync_out is a pulse of one clock cycle generated when the internal
PWM counter (re)starts. The signal trans_enable_out is a pulse synchronous to sync_out,
generated if a transfer from system registers to PWM shadow registers occurred when the
PWM counter restarted. A delay may be inserted between the counter start and
generation of trans_enable_out and sync_out.
A PWM module can use input signals trans_enable_in and sync_in to synchronize its
internal PWM counter and the transfer of shadow registers (Slave mode).
Each of the four PWM modules in the MSCSS has the following pins. These are combined
with other functions on the port pins of the LPC2921/2923/2925.
PWM0 to PWM3 pins (n = 0 to 3).
Table 21.
The PWM modules are clocked by CLK_MSCSS_PWMx (x = 0 to 3), see
Note that each PWM has its own CLK_MSCSS_PWMx branch clock for power
management. The frequency of all these clocks is identical to CLK_MSCSS_APB since
they are derived from the same base clock BASE_MSCSS_CLK.
Also note that unlike the timer modules in the Peripheral SubSystem, the actual timer
counter registers of the PWM modules run at the same clock as the APB system interface
CLK_MSCSS_APB. This clock is independent of the AHB system clock.
If a PWM module is not used its CLK_MSCSS_PWMx branch clock can be switched off.
The two timers in the MSCSS are functionally identical to the timers in the peripheral
subsystem, see
the timers in the peripheral subsystem, but the capture inputs and match outputs are not
available on the device pins. These signals are instead connected to the ADC and PWM
modules as outlined in the description of the MSCSS, see
See
Symbol
PWMn CAP[0]
PWMn CAP[1]
PWMn CAP[2]
PWMn MAT[0]
PWMn MAT[1]
PWMn MAT[2]
PWMn MAT[3]
PWMn MAT[4]
PWMn MAT[5]
PWMn TRAP
Section 6.12.3
PWM pins
All information provided in this document is subject to legal disclaimers.
Section
Pin name
PCAPn[0]
PCAPn[1]
PCAPn[2]
PMATn[0]
PMATn[1]
PMATn[2]
PMATn[3]
PMATn[4]
PMATn[5]
TRAPn
for a functional description of the timers.
Rev. 03 — 14 April 2010
6.12.3. The features of the timers in the MSCSS are the same as
Direction
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
ARM9 microcontroller with CAN, LIN, and USB
Description
PWMn capture input 0
PWMn capture input 1
PWMn capture input 2
PWMn match output 0
PWMn match output 1
PWMn match output 2
PWMn match output 3
PWMn match output 4
PWMn match output 5
PWMn trap input (on the LPC2921/2923/2925
n = 2, 3)
LPC2921/2923/2925
Section
Table 21
6.14.1.
© NXP B.V. 2010. All rights reserved.
shows the
Section
6.7.2.
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