LPC2925FBD100,551 NXP Semiconductors, LPC2925FBD100,551 Datasheet - Page 28

• Manufacturer Part Number: LPC2925FBD100,551
• Description: IC ARM9 MCU FLASH 512KB 100-LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2900r

Specifications of LPC2925FBD100,551

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 125MHz
• Connectivity: CAN, I²C, LIN, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 16K x 8
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 16x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: LPC29
• Core: ARM968E-S
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935287116551

NXP Semiconductors
LPC2921_23_25_3
Product data sheet
6.12.5.3 Clock description
6.12.6.1 Functional description
6.12.6.2 Pin description
6.12.6 General-purpose I/O
The SPI modules are clocked by two different clocks; CLK_SYS_PESS and CLK_SPIx
(x = 0, 1, 2), see
power management. The frequency of all clocks CLK_SPIx is identical as they are derived
from the same base clock BASE_CLK_SPI. The register interface towards the system bus
is clocked by CLK_SYS_PESS. The serial-clock rate divisor is clocked by CLK_SPIx.
The SPI clock frequency can be controlled by the CGU. In master mode the SPI clock
frequency (CLK_SPIx) must be set to at least twice the SPI serial clock rate on the
interface. In slave mode CLK_SPIx must be set to four times the SPI serial clock rate on
the interface.
The LPC2921/2923/2925 contains two general-purpose I/O ports located at different
peripheral base addresses. All I/O pins are bidirectional, and the direction can be
programmed individually. The I/O pad behavior depends on the configuration
programmed in the port function-select registers.
The key features are:
The general-purpose I/O provides individual control over each bidirectional port pin. There
are two registers to control I/O direction and output level. The inputs are synchronized to
achieve stable read-levels.
To generate an open-drain output, set the bit in the output register to the desired value.
Use the direction register to control the signal. When set to output, the output driver
actively drives the value on the output. When set to input, the signal floats and can be
pulled up internally or externally.
The five GPIO ports in the LPC2921/2923/2925 have the pins listed below. The GPIO pins
are combined with other functions on the port pins of the LPC2921/2923/2925.
shows the GPIO pins.
Table 16.
Symbol
GPIO0 pin[31:0]
GPIO1 pin[27:0]
GPIO5 pin[19:18]
•
•
•
•
General-purpose parallel inputs and outputs.
Direction control of individual bits.
Synchronized input sampling for stable input-data values.
All I/O pins default to input at reset to avoid any possible bus conflicts.
GPIO pins
All information provided in this document is subject to legal disclaimers.
Section
Pin name
P0[31:0]
P1[27:0]
P5[19:18]
Rev. 03 — 14 April 2010
6.7.2. Note that each SPI has its own CLK_SPIx branch clock for
Direction
IN/OUT
IN/OUT
IN/OUT
ARM9 microcontroller with CAN, LIN, and USB
Description
GPIO port x pins 31 to 0
GPIO port x pins 27 to 0
GPIO port x pins 19 and 18
LPC2921/2923/2925
© NXP B.V. 2010. All rights reserved.
Table 16
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