HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 103
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 103 of 980
- Download datasheet (6Mb)
Note:
Instruction
DT
EXTS.B
EXTS.W
EXTU.B
EXTU.W
MAC.L
MAC.W
MUL.L
MULS.W
MULU.W
NEG
NEGC
SUB
SUBC
SUBV
*
Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
@Rm+,
@Rn+
@Rm+,
@Rn+
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
The number of execution cycles indicated within the parentheses ( ) are required when
the operation result is read from the MACH/MACL register immediately after the
instruction.
Instruction Code
0100nnnn00010000
0110nnnnmmmm1110
0110nnnnmmmm1111
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm1111
0100nnnnmmmm1111
0000nnnnmmmm0111
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
0011nnnnmmmm1011
Operation
Rn – 1 → Rn, if Rn = 0, 1 → T,
else 0 → T
A byte in Rm is sign-extended
→ Rn
A word in Rm is sign-extended
→ Rn
A byte in Rm is zero-extended
→ Rn
A word in Rm is zero-extended
→ Rn
Signed operation of (Rn) ×
(Rm) + MAC → MAC,Rn + 4
→ Rn, Rm + 4 → Rm,
32 × 32 + 64 → 64 bits
Signed operation of (Rn) ×
(Rm) + MAC → MAC,Rn + 2
→ Rn, Rm + 2 → Rm,
16 × 16 + 64 → 64 bits
Rn × Rm → MACL,
32 × 32 → 32 bits
Signed operation of Rn × Rm
→ MACL,
16 × 16 → 32 bits
Unsigned operation of
Rn × Rm → MACL,
16 × 16 → 32 bits
0–Rm→Rn
0–Rm–T→Rn, Borrow→T
Rn–Rm→Rn
Rn–Rm–T→Rn, Borrow →T
Rn–Rm→Rn, Underflow→T
Rev. 1.00 Dec. 27, 2005 Page 59 of 932
Privileged
Mode
Cycles
1
1
1
1
1
2 (to 5)*
2 (to 5)*
2 (to 5)*
1( to 3)*
1(to 3)*
1
1
1
1
1
REJ09B0269-0100
Section 2 CPU
T Bit
Comparison
result
Borrow
Borrow
Underflow
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