HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 477
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 477 of 980
- Download datasheet (6Mb)
Figure 12.27 shows the access timing in low-frequency mode. In this mode, commands, addresses,
and write data are output in synchronization with the falling edge of CKIO, which is half a cycle
delayed than the normal timing. Read data is fetched at the rising edge of CKIO, which is half a
cycle faster than the normal timing. This timing allows the hold time of commands, addresses,
write data, and read data to be extended.
If SDRAM is operated at a high frequency with the SLOW bit set to 1, the setup time of
commands, addresses, write data, and read data are not guaranteed. Take the operating frequency
and timing design into consideration when making the SLOW bit setting.
Power-Down Mode: If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in the power-
down mode by bringing the CKE signal to the low level in the non-access cycle. This power-down
mode can effectively lower the power consumption in the non-access cycle. However, please note
A12/A11*
A25 to A0
D31 to D0
DACKn*
RD/WR
DQMxx
CKIO
CKE
RAS
CAS
CSn
BS
1
2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
Tr
2. The waveform for DACKn is when active low is specified.
Figure 12.27 Access Timing in Low-Frequency Mode
Tc1
Td1
Tde
Tap
(High)
Tr
Rev. 1.00 Dec. 27, 2005 Page 433 of 932
Tc1
Section 12 Bus State Controller (BSC)
Tnop
Trwl
REJ09B0269-0100
Tap
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