HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 767

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

18.4.8
The EtherC has a function to change the non-transmission period IPG (Inter Packet Gap) between
transmit frames. By changing the set values of the IPG setting register (IPGR), the transmission
efficiency can be raised and lowered from the standard value. IPG settings are prescribed in
IEEE802.3 standards. When changing settings, adequately check that the respective devices can
operate smoothly on the same network.
18.4.9
The EtherC supports IEEE802.1Q frame processing. It can add or delete Qtags to or from frames
processed in relay. This function can also transmit and receive QoS frames. During relaying, if the
Ethernet device connected to one MAC controller cannot transmit or receive QoS frames, it can be
converted to the normal IEEE802.3 frames and relayed in this LSI. Whether to add or delete Qtags
is determined by the added Qtag value set register (TSU_ADQT0/1). Figure 18.11 shows an
outline of the Qtag add function while figure 18.12 shows the comparison between the normal
Ethernet frames and IEEE802.1Q frames (with Qtag). For details on setting Qtag, refer to the
specifications on Qtag control specified in IEEE802.1Q.
(short IPG)
(long IPG)
Case A
Case B
Operation by IPG Setting
Direction for IEEE802.1Q Qtag
Note: * IPG may be longer than the set value, depending on the state of the line and the system bus.
Figure 18.10 Changing IPG and Transmission Efficiency
Packet
[1]
[1]
IPG*
[2]
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Rev. 1.00 Dec. 27, 2005 Page 723 of 932
Section 18 Ethernet Controller (EtherC)
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REJ09B0269-0100
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