HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 607

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
Data Transfer Operations:
The SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE
and RE bits in SCSCR to 0, then initialize the SCIF as described below.
When the transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making
the change using the following procedure. When the TE bit is cleared to 0, SCTSR is initialized.
Note that clearing the TE and RE bits to 0 does not change the contents of SCFSR, SCFTDR, or
SCFRDR. The TE bit should be cleared to 0 after all transmit data has been sent and the TEND bit
in SCFSR has been set to 1. Clearing to 0 can also be performed during transmission, but the data
being transmitted will go to the high-impedance state after the clearance. Before setting TE to 1
again to start transmission, the TFRST bit in SCFCR should first be set to 1 to reset SCFTDR.
When an external clock is used, the clock should not be stopped during operation including
initialization because its operation becomes unreliable.
Figure 16.3 shows a sample the SCIF initialization flowchart.
Rev. 1.00 Dec. 27, 2005 Page 563 of 932
REJ09B0269-0100