HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 45
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 45 of 980
- Download datasheet (6Mb)
This LSI is a 32-bit reduced instruction set computer (RISC) microprocessor that is built on the
SuperH architecture.
Its core is a RISC-type CPU with a Digital Signal Processor (DSP) as a functional extension. A
single chip microprocessor integrates peripheral functions required for building an Ethernet
system.
The LSI comprises two channels of Ethernet controllers. They include a media access controller
(MAC) and a media independent interface (MII) standard unit that conforms to the IEE802.3u
standard and provide 10/100 Mbps LAN connection.
The LSI has a large capacity (32-kbyte) cache memory, 16-kbyte on-chip X/Y memory, and an
interrupt controller for system configuration to enable flexible system design. It supports high-
speed data transfer using an on-chip direct memory access controller (DMAC). Its external
memory access support provides direct connection to various types of memory.
The strong on-chip power saving function reduces power consumption even during high-speed
operation.
1.1
The features of this LSI are shown below.
CPU:
• Original Renesas-Technology SuperH architecture
• Compatible with SH-1, SH-2, and SH-3 at object code level
• 32-bit internal data bus
• Various groups of built-in registers
• Supports RISC-type instruction set
• Instruction execution time: one instruction/cycle for basic instructions
• Logical address space: 4 Gbytes
General registers: Sixteen 32-bit registers (including eight 32-bit bank registers)
Control registers: Five 32-bit registers
System registers: Four 32-bit registers
Instruction length: 16-bit fixed length for improved code efficiency
Load/store architecture
Delayed branch instructions
Instruction set based on C language
Features
Section 1 Overview and Pin Function
Rev. 1.00 Dec. 27, 2005 Page 1 of 932
Section 1 Overview and Pin Function
REJ09B0269-0100
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