HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 684

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 18 Ethernet Controller (EtherC)
Notes: 1. MII signal conforming to IEEE802.3u
Rev. 1.00 Dec. 27, 2005 Page 640 of 932
REJ09B0269-0100
Name
Transmit enable
Transmit data
Transmit error
Receive data valid
Receive data
Receive error
Carrier detection
Collision detection
Management data
clock
Management data
I/O
Link status
General-purpose
external output
Wake-On-LAN
CAM input 0
CAM input 1
Bus release request 
2. The CAM input signal function is set by the CAMSEL03 to CAMSEL00 and CAMSEL13
3. Refer to section 19, Ethernet Controller Direct Memory Access Controller (E-DMAC)
to CAMSEL10 in the TSU_FWSLC register.
and section 19.2.18, Overflow Alert FIFO Threshold Register (FCFTR).
1
1
Port
1
1
1
1
1
1
1
1
1
1
1


TX-EN1*
ETXD13 to
ETXD10*
TX-ER1*
RX-DV1*
ERXD13 to
ERXD10*
RX-ER1*
CRS1*
COL1*
MDC1*
MDIO1*
EXOUT1
WOL1
CAMSEN0*
CAMSEN1*
ARBUSY*
Abbreviation I/O
LKNSTA1
1
1
1
1
1
1
1
1
1
1
3
2
2
O
O
O
I
I
I
I
I
O
I/O
I
O
O
I
I
O
Function
Indicates that transmit data is ready on
ETXD3 to ETXD0
4-bit transmit data
Notifies PHY-LSI of error during
transmission
Indicates that valid receive data is on
ERXD3 to ERXD0
4-bit receive data
Identifies error state occurred during data
reception
Carrier detection signal
Collision detection signal
Reference clock signal for information
transfer via MDIO
Bidirectional signal for exchange of
management information between this LSI
and PHY
Inputs link status from PHY
Signal indicating value of register-bit
(ECMR1-ELB)
Signal indicating reception of Magic Packet
CAM interface signal input 0
CAM interface signal input 1
Signal indicating bus release request when
the threshold value set for the data volume
in the receive FIFO has been exceeded