HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 617

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
In clock synchronous mode, the SCIF receives data in synchronization with the rise of the serial
clock.
Data Transfer Format: A fixed 8-bit data format is used. No parity bit is added.
Clock: An internal clock generated by the on-chip baud rate generator or an external synchronous
clock input from the SCIFnCK pin can be selected, according to the setting of the C/A bit in
SCSMR and bits CKE1 and CKE0 in SCSCR. For details, see table 16.4.
When the SCIF is operated on an internal clock, synchronous clock is output from the SCIFnCK
pin. Eight serial clock pulses are output in the transfer of one character, and when no
transmission/reception is performed the clock is fixed high. If an internal clock is selected when
only reception is performed, clock pulse is output continuously until the number of data bytes in
the receive FIFO reaches the receive trigger set number while the RE bit in SCSCR is 1.
Data Transfer Operations:
The SCIF Initialization: Before transmitting and receiving data, it is necessary to clear the TE
and RE bits in SCSCR to 0, then initialize the SCIF as described below.
When the mode, communication format etc., is changed, the TE and RE bits must be cleared to 0
before making the change using the following procedure. When the TE bit is cleared to 0, SCTSR
is initialized. Note that the RDF, PER, FER, and ORER flags and contents of SCFRDR are
retained even if the RE bit is cleared to 0.
Rev. 1.00 Dec. 27, 2005 Page 573 of 932
REJ09B0269-0100