HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 162

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 DSP Operating Unit
3.5.4
Figure 3.9 shows the ALU arithmetic operation flow. Table 3.21 shows the variation of this type
of operation and table 3.22 shows the correspondence between each operand and registers.
Note: The ALU fixed-point arithmetic operations are basically 40-bit operation; 32 bits of the
ALU fixed-point operations are executed between registers. Each source and destination operand
are selected independently from one of the DSP registers. When a register providing guard bits is
specified as an operand, the guard bits are activated for this type of operation. These operations
are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the
MA stage in which memory access is performed.
Rev. 1.00 Dec. 27, 2005 Page 118 of 1044
REJ09B0269-0100
base precision and 8 bits of the guard-bit parts. So the signed bit is copied to the guard-bit
parts when a register not providing the guard-bit parts is specified as the source operand.
When a register not providing the guard-bit parts is specified as a destination operand, the
lower 32 bits of the operation result are input into the destination register.
ALU Fixed-Point Operations
39
Guard
31
Source 1
Figure 3.9 ALU Fixed-Point Arithmetic Operation Flow
39
Guard
31
Destination
0
ALU
39
Guard
31
Source 2
0
DSR
0
GT Z
N
V DC