HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 375
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 375 of 980
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The bus state controller (BSC) outputs control signals for various types of memory that is
connected to the external address space and external devices. The BSC functions enable this LSI
to connect directly with SRAM, SDRAM, and other memory storage devices, and external
devices.
12.1
The BSC has the following features:
1. External address space
• A maximum 32 or 64 Mbytes for each of the eight areas, CS0, CS2 to CS4, CS5A, CS5B,
• A maximum 64 Mbytes for each of the six areas, CS0, CS2 to CS4, CS5, and CS6, totally a
• Can specify the normal space interface, byte-selection SRAM, burst ROM (clock synchronous
• Can select the data bus width (8, 16, or 32 bits) for each address space.
• Controls the insertion of the wait state for each address space.
• Controls the insertion of the wait state for each read access and write access.
• Can set the independent idling cycle in the continuous access for five cases: read-write (in
2. Normal space interface
• Supports the interface that can directly connect to the SRAM.
3. Burst ROM (clock asynchronous) interface
• High-speed access to the ROM that has the page mode function.
4. SDRAM interface
• Can set the SDRAM in up to 2 areas.
• Multiplex output for row address/column address.
• Efficient access by single read/single write.
• High-speed access by bank-active mode.
• Supports an auto-refresh and self-refresh.
CS6A and CS6B, totally 384 Mbytes (divided into eight areas).
total of 384 Mbytes (divided into six areas).
or asynchronous), SDRAM, PCMCIA for each address space.
same space/different space), read-read (in same space/different space), or the first cycle is a
write access.
Features
Section 12 Bus State Controller (BSC)
Rev. 1.00 Dec. 27, 2005 Page 331 of 932
Section 12 Bus State Controller (BSC)
REJ09B0269-0100
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