HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 509
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 509 of 980
- Download datasheet (6Mb)
Bit
22
21 to
18
17
16
Bit Name
TL
AM
AL
Initial
Value
0
All 0
0
0
R/W
R/W
R
R/W
R/W
Description
Transfer End Level
Specifies the TEND signal output is high active or low
active.
This bit is valid only in CHCR0 and CHCR1.This bit is
reserved and always read as 0 in CHCR2 to CHCR5. The
write value should always be 0.
0: Low-active output of TEND
1: High-active output of TEND
Reserved
These bits are always read as 0. The write value should
always be 0.
Acknowledge Mode
Specifies whether the DACK is output in data read cycle or
in data write cycle in dual address mode.
In single address mode, the DACK is always output
regardless of the specification by this bit.
This bit is valid only in CHCR0 and CHCR1.This bit is
reserved and always read as 0 in CHCR2 to CHCR5. The
write value should always be 0.
0: DACK output in read cycle (Dual address mode)
1: DACK output in write cycle (Dual address mode)
Acknowledge Level
Specifies the DACK signal output is high active or low
active.
This bit is valid only in CHCR0 and CHCR1.This bit is
reserved and always read as 0 in CHCR2 to CHCR5. The
write value should always be 0.
0: Low-active output of DACK
1: High-active output of DACK
Section 13 Direct Memory Access Controller (DMAC)
Rev. 1.00 Dec. 27, 2005 Page 465 of 932
REJ09B0269-0100
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