HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 90
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 90 of 980
- Download datasheet (6Mb)
Section 2 CPU
Rev. 1.00 Dec. 27, 2005 Page 46 of 932
REJ09B0269-0100
Addressing
Mode
Register
indirect with
pre-decrement
Register
indirect with
displacement
Indexed
register indirect
GBR indirect
with
displacement
Instruction
Format
@–Rn
@(disp:4,
Rn)
@(R0, Rn)
@(disp:8,
GBR)
Effective Address Calculation Method
Effective address is register Rn
contents, decremented by a constant
beforehand: 1 for a byte operand, 2 for a
word operand, 4 for a longword
operand.
Effective address is register Rn contents
with 4-bit displacement disp added. After
disp is zero-extended, it is multiplied by
1 (byte), 2 (word), or 4 (longword),
according to the operand size.
Effective address is sum of register Rn
and R0 contents.
Effective address is register GBR
contents with 8-bit displacement disp
added. After disp is zero-extended, it is
multiplied by 1 (byte), 2 (word), or 4
(longword), according to the operand
size.
(zero-extended)
(Zero-extended)
1/2/4
1/2/4
1/2/4
disp
Rn
R0
GBR
disp
Rn
Rn
Rn - 1/2/4
×
×
+
+
+
-
+ disp × 1/2/4
+ disp × 1/2/4
Rn - 1/2/4
Rn + R0
GBR
Rn
Byte: Rn – 1 → Rn
Word: Rn – 2 → Rn
Longword: Rn – 4 → Rn
(Instruction executed with
Rn after calculation)
Byte: Rn + disp
Word: Rn + disp × 2
Longword: Rn + disp × 4
Rn + R0
Byte: GBR + disp
Word: GBR + disp × 2
Longword: GBR + disp ×
4
Calculation Formula
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