HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 511

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
11
10
9
8
7
6
5
Bit Name
RS3
RS2
RS1
RS0
DL
DS
TB
Initial
Value
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Resource Select
Specify which transfer requests will be sent to the DMAC.
The change of transfer request source should be done in the
state that the DMA enable bit (DE) is cleared to 0.
0000: External request, dual address mode
0010: External request, single address mode
0011: External request, single address mode
0100: Auto request
1000: DMA extension resource selector
Other than above: Reserved (setting prohibited)
Note: An external request specification is valid only in
DREQ Level and DREQ Edge Select
Specify the sampling method of the DREQ pin input and the
sampling level.
These bits are valid only in CHCR0 and CHCR1. These bits
are reserved and always read as 0 in CHCR2 to CHCR5.
The write value should always be 0.
In channels 0 and 1, also, if the transfer request source is
specified as an on-chip peripheral module or if an auto-
request is specified, the specification by this bit is invalid.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
Transfer Bus Mode
Specifies the bus mode when the DMA transfers data.
0: Cycle steal mode
1: Burst mode
CHCR0 and CHCR1. None of the external request
specification can be selected in CHCR2 to CHCR5.
External address space → external device with DACK
External device with DACK → external address space
Section 13 Direct Memory Access Controller (DMAC)
Rev. 1.00 Dec. 27, 2005 Page 467 of 932
REJ09B0269-0100