HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 528
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 528 of 980
- Download datasheet (6Mb)
Section 13 Direct Memory Access Controller (DMAC)
2. Single Address Mode
Rev. 1.00 Dec. 27, 2005 Page 484 of 932
REJ09B0269-0100
Figure 13.6 Example of DMA Transfer Timing in Dual Address Mode (Source: Ordinary
In single address mode, either the transfer source or transfer destination external device is
accessed (selected) by means of the DACK signal, and the other device is accessed by address.
In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the
external devices by outputting the DACK transfer request acknowledge signal to it, and at the
same time outputting an address to the other device involved in the transfer. For example, in
the case of transfer between external memory and an external device with DACK shown in
figure 13.7, when the external device outputs data to the data bus, that data is written to the
external memory in the same bus cycle.
(Active-Low)
D31 to D0
A25 to A0
DACKn
CKIO
WEn
CSn
Note: In transfer between external memories, with DACK output in the read cycle,
RD
DACK output timing is the same as that of CSn.
memory, Destination: Ordinary memory)
Data read cycle
Transfer source
(1st cycle)
address
Data write cycle
Transfer destination
(2nd cycle)
address
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