HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 38
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 38 of 980
- Download datasheet (6Mb)
Figure 24.59 MII Transmit Timing (Normal Operation)............................................................ 909
Figure 24.60 MII Transmit Timing (Case of Conflict)............................................................... 909
Figure 24.61 MII Receive Timing (Normal Operation) ............................................................. 910
Figure 24.62 MII Receive Timing (Case of Error) ..................................................................... 910
Figure 24.63 MDIO Input Timing .............................................................................................. 910
Figure 24.64 MDIO Output Timing ........................................................................................... 910
Figure 24.65 WOL Output Timing ............................................................................................. 911
Figure 24.66 EXOUT Output Timing......................................................................................... 911
Figure 24.67 CAMSEN Input Timing ........................................................................................ 911
Figure 24.68 ARBUBY Output Timing ..................................................................................... 911
Figure 24.69 I/O Port Timing ..................................................................................................... 912
Figure 24.70 TCK Input Timing................................................................................................. 913
Figure 24.71 TRST Input Timing (Reset Hold).......................................................................... 914
Figure 24.72 H-UDI Data Transfer Timing................................................................................ 914
Figure 24.73 ASEMD0 Input Timing......................................................................................... 914
Figure 24.74 ASEBRKAK Delay Time ..................................................................................... 914
Figure 24.75 Output Load Circuit .............................................................................................. 915
Figure 24.76 Load Capacitance vs. Delay Time......................................................................... 916
Appendix
Figure B.1 Package Dimensions (HQFP2828-256 (FP-256G/GV))........................................... 926
Figure B.2 Package Dimensions (P-LFBGA1717-256 (BP-256H/HV)) .................................... 927
Rev. 1.00 Dec. 27, 2005 Page xxxvi of xlii
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