HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 125
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 125 of 980
- Download datasheet (6Mb)
• Example 4: Repeat loop consisting of one instruction
In repeat loops consisting of three instructions, two instructions and one instruction, specific
addresses are specified in the RS register. RE – RS is calculated during SETRC instruction
execution, and the number of instructions included in the repeat loop is determined according to
the result. A value of 0, –2,and –4 in the result correspond to 3 instructions, two instructions, and
one instruction, respectively.
If repeat instruction execution is completed without branching and if RC[11:0]>0, an instruction
following the repeat detection instruction is regarded as a repeat start instruction and instruction
execution is repeated for the number of times corresponding to the recognized number of
instructions. If RC[11:0] ≥ 2 when the repeat end instruction is completed, the RC[11:0] is
decremented by 1 and then control is passed to the address specified by the RS register. If
RC[11:0] ==1(or 0) when the repeat end instruction is completed, the RC[11:0] is cleared to 0 and
then the control is passed to the next instruction following the repeat end instruction.
Note: If RE – RS is a positive value, the CPU regards the repeat loop as a four-instruction repeat
RptDtct:
RptStart:
RptEnd:
loop. (In a repeat loop consisting of four or more instructions, RE – RS is always a
positive value. For details, refer to example 1 above.) If RE – RS is positive, or a value
other than 0, –2,and –4, correct operation cannot be guaranteed.
LDRS RptStart +8
LDRE RptStart +4
SETRC #4
instr0
instr1
; Sets (repeat detection instruction
; Sets (repeat detection instruction
; Sets the number of repetitions (4) to
; If RE-RS==-4 during SETRC instruction
; An instruction prior to the Repeat
; [Repeat start instruction] ==
address + 8) to the RS register
address + 4) to the RE register
the RC[11:0] bits of the SR register
execution, the repeat loop is regarded
as one-instruction repeat.
start instruction is regarded as a
repeat detection instruction.
[Repeat end instruction]
Rev. 1.00 Dec. 27, 2005 Page 81 of 1044
Section 3 DSP Operating Unit
REJ09B0269-0100
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