HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 66
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 66 of 980
- Download datasheet (6Mb)
Section 1 Overview and Pin Function
Rev. 1.00 Dec. 27, 2005 Page 22 of 932
REJ09B0269-0100
Classification
Bus control
Direct memory
access controller
(DMAC)
Symbol
WE0(BE0)
RAS
CAS
CKE
IOIS16
DQMUU
DQMUL
DQMLU
DQMLL
REFOUT
WAIT
DREQ0,
DREQ1
DACK0,
DACK1
TEND0,
TEND1
I/O
O
O
O
O
I
O
O
O
O
O
I
I
O
O
Name
Byte write
RAS
CAS
CK enable
16-bit I/O
selection
DQM
DQM
DQM
DQM
Refresh request
output
Wait
DMA-transfer
request
DMA-transfer
request accept
DMA-transfer
end output
Function
Indicates that bits 7 to 0 of the data
in the external memory or device are
being written.
Connects RAS pin during access to
the SDRAM.
Connects CAS pin during access to
the SDRAM.
Connects CKE pin during access to
the SDRAM.
Indicates 16-bit I/O for PCMCIA.
Selects D31 to D24 during access to
the SDRAM.
Selects D23 to D16 during access to
the SDRAM.
Selects D15 to D8 during access to
the SDRAM.
Selects D7 to D0 during access to
the SDRAM.
Outputs the refresh request in
master mode or bus release.
Inserts a wait cycle into the bus
cycles during access to the external
space.
Input pin for external requests for
DMA transfer.
Output pin for request acceptance,
in response to external requests for
DMA transfer.
Output pin for DMA transfer end
signal.
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