HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 210
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 210 of 980
- Download datasheet (6Mb)
Section 4 Exception Handling
4.3.2
CPU address error:
• Conditions
• Types
• Save address
• Exception code
• Remarks
Illegal general instruction exception:
• Conditions
Note: For details on undefined code, refer to table 2.12 in section 2.6.2, Operation Code Map.
Rev. 1.00 Dec. 27, 2005 Page 166 of 932
REJ09B0269-0100
Instruction is fetched from odd address (4n + 1, 4n + 3)
Word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3)
Longword is accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
The area ranging from H'80000000 to H'FFFFFFFF in logical space is accessed in user
Instruction synchronous, re-execution type
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
An exception occurred during read: H′0E0
An exception occurred during write: H′100
The logical address (32 bits) that caused the exception is set in TEA.
When undefined code not in a delay slot is decoded
When a privileged instruction not in a delay slot is decoded in user mode
4n + 3)
mode
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions.
When an undefined code other than H′FC00 to H′FFFF is decoded, operation cannot be
guaranteed.
General Exceptions
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