HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 259
![MPU 1.5/3.3V 0K PB-FREE 256-BGA](/photos/28/61/286175/256-lfbga_sml.jpg)
HD6417712BPV
Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet
1.HD6417712BPV.pdf
(980 pages)
Specifications of HD6417712BPV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 259 of 980
- Download datasheet (6Mb)
6.1
• Capacity: 16 or 32 kbytes
• Structure: Instructions/data mixed, 4-way set associative
• Locking: Way 2 and way 3 are lockable
• Line size: 16 bytes
• Number of entries: 256 entries/way in 16-kbyte mode to 512 entries/way in 32-kbyte mode
• Write system: Write-back/write-through is selectable for spaces P0, P1, P3, and U0
• Replacement method: Least-recently used (LRU) algorithm
Note: After power-on reset or manual reset, initialized as 16-kbyte mode (256 entries/way).
6.1.1
The cache mixes instructions and data and uses a 4-way set associative system. It is composed of
four ways (banks), and each of which is divided into an address section and a data section.
Each of the address and data sections is divided into 512 entries. The entry data is called a line.
Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 8 kbytes (16 bytes × 512
entries) in the cache as a whole (4 ways). The cache capacity is 32 kbytes as a whole. Figure 6.1
shows the cache structure.
Entry 511
Features
Cache Structure
Entry 0
Entry 1
.
.
.
.
.
.
24 (1 + 1 + 22) bits
V U Tag address
Address array (ways 0 to 3)
Figure 6.1 Cache Structure
Section 6 Cache
511
0
1
.
.
.
.
.
.
LW0
LW0 to LW3: Longword data 0 to 3
128 (32 × 4) bits
LW1
LW2
Data array (ways 0 to 3)
Rev. 1.00 Dec. 27, 2005 Page 215 of 932
LW3
511
0
1
.
.
.
.
.
.
REJ09B0269-0100
Section 6 Cache
LRU
6 bits
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