HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 668

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 17 Serial I/O with FIFO (SIOF)
Reception in Master Mode: Figure 17.10 shows an example of settings and operation for master
mode reception.
Rev. 1.00 Dec. 27, 2005 Page 624 of 932
REJ09B0269-0100
No.
2
4
1
3
5
6
7
8
9
Output SITDR contents from TXD_SIO
Start SCK_SIO clock transmission
Figure 17.9 Example of Transmission Operation in Master Mode
synchronously with SIOFSYNC
SIRDAR, SICDAR, and SIFCTR
Set SIMDR, SISCR, SITDAR,
Set SCKE bit in SICTR to 1
Clear TXE bit in SICTR to 0
Set FSE bit in SICTR to 1
Set TXE bit in SICTR to 1
Time Chart
TDREQ=1?
Set SITDR
Transfer
ended?
Start
End
Yes
Yes
No
No
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and the upper limit value of FIFO
request
Set operation start for baud rate
generator
Set the start for frame
synchronous signal
Set to enable transmission
Set transmit data
Set to disable transmission
SIOF Settings
End transmission
Transmit
Transmit frame
synchronous signal
Submit transmission
request
Output serial clock
SIOF Operation

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