UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 128

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

126
MCC = 1
Notes 1.
CPU clock: f
f
f
XP
R
CSS = 1
oscillation
CPU clock: f
: Oscillating/
f
: Oscillation
XP
Status 6
f
stopped
stopped
R
: Oscillating/
oscillation
: Oscillating
Status 5
stopped
2.
3.
4.
5.
6.
Note 5
(2) When “internal oscillator can be stopped by software” is selected by option byte
MCC = 0
XT
When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register
(MCM) is 1.
Before shifting from status 2 to status 3 after reset and STOP are released, check the high-speed
system clock oscillation stabilization time status using the oscillation stabilization time counter status
register (OSTC).
When shifting from status 2 to status 1, make sure that MCS is 0.
When “internal oscillator can be stopped by software” is selected by the option byte, the clock supply
to the watchdog timer is stopped after the HALT or STOP instruction has been executed, regardless
of the setting of bit 0 (RSTOP) of the internal oscillation mode register (RCM) and bit 0 (MCM0) of the
main clock mode register (MCM).
The operation cannot be shifted between subsystem clock operation and internal oscillation clock
operation.
All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
XT
CSS = 0
CPU clock: f
f
XP
f
R
: Oscillating
: Oscillation
Status 4
stopped
Note 5
HALT
instruction
XP
Figure 5-13. Status Transition Diagram (2/4)
RSTOP = 1
RSTOP = 0
Interrupt
HALT
instruction
CHAPTER 5 CLOCK GENERATOR
(when subsystem clock is used)
Interrupt
Note 1
User’s Manual U16899EJ3V0UD
CPU clock: f
f
f
XP
R
instruction
: Oscillating
Interrupt
: Oscillating
Status 3
STOP
HALT
instruction
XP
Interrupt
MCM0 = 1
STOP
HALT
MCM0 = 0
instruction
Interrupt
Note 4
Note 4
STOP
Note 2
f
CPU clock: f
f
XP
R
: Oscillating
: Oscillating
Status 2
Interrupt
HALT
instruction
HALT
instruction
R
STOP
instruction
Reset
MSTOP = 1
Interrupt
MSTOP = 0
Reset release
Interrupt
Note 6
Note 3
CPU clock: f
f
f
R
XP
: Oscillating
Status 1
: Oscillation
stopped
R