UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 548

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

546
8-bit
timer/
event
counters
50, 51
(TM50,
TM51)
8-bit
timers H0,
H1
(TMH0,
TMH1)
Function
CR5n: 8-bit
timer compare
register 5n
TCL50: Timer
clock selection
register 50
TCL51: Timer
clock selection
register 51
TMC5n: 8-bit
timer mode
control register
5n
Interval
timer/square
waveform
output
PWM output
Timer start error An error of up to one clock may occur in the time required for a match signal to be
CMP0n: 8-bit
timer H
compare
register 0n
CMP1n: 8-bit
timer H
compare
register 1n
TMHMD0: 8-bit
timer H mode
register 0
Details of
Function
In the mode in which clear & start occurs on a match of TM5n and CR5n
(TMC5n6 = 0), do not write other values to CR5n during operation.
In PWM mode, make the CR5n rewrite interval 3 count clocks of the count clock
(clock selected by TCL5n) or more.
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the count clock is the internal oscillation clock, the operation of 8-bit timer/event
counter 50 is not guaranteed.
When rewriting TCL50 to other data, stop the timer operation beforehand.
Be sure to clear bits 3 to 7 to 0.
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the count clock is the internal oscillation clock, the operation of 8-bit timer/event
counter 51 is not guaranteed.
When rewriting TCL51 to other data, stop the timer operation beforehand.
Be sure to clear bits 3 to 7 to 0.
The settings of LVS5n and LVR5n are valid in other than PWM mode.
Perform <1> to <4> below in the following order, not at the same time.
<1> Set TMC5n1, TMC5n6: Operation mode setting
<2> Set TOE5n to enable output: Timer output enable
<3> Set LVS5n, LVR5n (see Caution 1): Timer F/F setting
<4> Set TCE5n
Stop operation before rewriting TMC5n6.
Do not write other values to CR5n during operation.
In PWM mode, make the CR5n rewrite interval 3 count clocks of the count clock
(clock selected by TCL5n) or more.
When reading from CR5n between <1> and <2> in Figure 7-15, the value read
differs from the actual value (read value: M, actual value of CR5n: N).
generated after timer start. This is because 8-bit timer counters 50 and 51
(TM50, TM51) are started asynchronously to the count clock.
CMP0n cannot be rewritten during timer count operation.
In the PWM output mode and carrier generator mode, be sure to set CMP1n
when starting the timer count operation (TMHEn = 1) after the timer count
operation was stopped (TMHEn = 0) (be sure to set again even if setting the
same value to CMP1n).
When the internal oscillation clock is selected as the clock to be supplied to the
CPU, the clock of the internal oscillator is divided and supplied as the count clock.
If the count clock is the internal oscillation clock, the operation of 8-bit timer H0 is
not guaranteed.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ3V0UD
Cautions
p. 184
p. 184
p. 185
p. 185
p. 185
p. 186
p. 186
p. 186
p. 188
p. 188
p. 188
pp. 190,
193
p. 194
p. 197
p. 198
p. 202
p. 202
p. 205
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