UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 410

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UPD78F0138HGK-9ET-A

Manufacturer Part Number
UPD78F0138HGK-9ET-A
Description
MCU 8BIT 60K FLASH 64TQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx1+r
Datasheet

Specifications of UPD78F0138HGK-9ET-A

Core Processor
78K/0
Core Size
8-Bit
Speed
16MHz
Connectivity
3-Wire SIO, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
42
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
22.4 Cautions for Power-on-Clear Circuit
voltage (V
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
software counter that uses a timer, and then initialize the ports.
408
Note 1
If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
In a system where the supply voltage (V
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
Notes 1.
POC
2.
), the system may be repeatedly reset and released from the reset status. In this case, the time from
No
If reset is generated again during this period, initialization processing is not started.
A flowchart is shown on the next page.
Figure 22-3. Example of Software Processing After Release of Reset (1/2)
50 ms has passed?
Change CPU clock
Check stabilization
Checking cause
(TMIFH1 = 1?)
(set to 50 ms)
of oscillation
of reset
Initialization
processing
Start timer
Reset
Power-on-clear
Yes
Note 2
CHAPTER 22 POWER-ON-CLEAR CIRCUIT
DD
User’s Manual U16899EJ3V0UD
) fluctuates for a certain period in the vicinity of the POC detection
; The internal oscillation clock is set as the CPU clock when
; The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
; 8-bit timer H1 can operate with the internal oscillation clock.
; Check the stabilization of oscillation of the high-speed system clock by using
; Change the CPU clock from the internal oscillation clock
; TMIFH1 = 1: Interrupt request is generated.
; Initialization of ports
the reset signal is generated
can be identified by the RESF register.
Source: f
(f
the OSTC register
to the high-speed system clock.
R
: internal oscillation clock frequency)
R
(480 kHz (MAX.))/2
Note 3
.
7
compare value 200 = 53 ms

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