UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 301

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UPD78F0138HGK-9ET-A

Manufacturer Part Number
UPD78F0138HGK-9ET-A
Description
MCU 8BIT 60K FLASH 64TQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx1+r
Datasheet

Specifications of UPD78F0138HGK-9ET-A

Core Processor
78K/0
Core Size
8-Bit
Speed
16MHz
Connectivity
3-Wire SIO, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
42
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
(2) Asynchronous serial interface reception error status register 6 (ASIS6)
Address: FF53H After reset: 00H R
Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of
Symbol
ASIS6
This register indicates an error status on completion of reception by serial interface UART6. It includes three
error flag bits (PE6, FE6, OVE6).
This register is read-only by an 8-bit memory manipulation instruction.
RESET input or clearing bit 7 (POWER6) or bit 5 (RXE6) of ASIM6 to 0 clears this register to 00H. 00H is read
when this register is read.
Figure 14-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)
2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop
3. If an overrun error occurs, the next receive data is not written to receive buffer register 6
4. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the
OVE6
asynchronous serial interface operation mode register 6 (ASIM6).
bits.
(RXB6) but discarded.
CPU is operating on the subsystem clock and the high-speed system clock is stopped. For
details, see CHAPTER 33 CAUTIONS FOR WAIT.
PE6
FE6
7
0
0
1
0
1
0
1
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
If the parity of transmit data does not match the parity bit on completion of reception
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
If the stop bit is not detected on completion of reception
If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
If receive data is set to the RXB6 register and the next reception operation is completed before the
data is read.
6
0
CHAPTER 14 SERIAL INTERFACE UART6
5
0
User’s Manual U16899EJ3V0UD
Status flag indicating framing error
Status flag indicating overrun error
Status flag indicating parity error
4
0
3
0
PE6
2
FE6
1
OVE6
0
299

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