UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 551
UPD78F0138HGK-9ET-A
Manufacturer Part Number
UPD78F0138HGK-9ET-A
Description
MCU 8BIT 60K FLASH 64TQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx1+r
Datasheet
1.UPD78F0138HGK-9ET-A.pdf
(568 pages)
Specifications of UPD78F0138HGK-9ET-A
Core Processor
78K/0
Core Size
8-Bit
Speed
16MHz
Connectivity
3-Wire SIO, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
42
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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A/D
converter
Function
ADM: A/D
converter mode
register
ADS: Analog
input channel
specification
register
ADCR: A/D
conversion result
register
PFM: Power-fail
comparison
mode register
PFT: Power-fail
comparison
threshold
register
A/D conversion
operation
Power-fail
detection
function
Operating
current in
standby mode
ANI0 to ANI7
input range
Conflict
operation
Details of
Function
If data is written to ADM, a wait cycle is generated. Do not write data to ADM
when the CPU is operating on the subsystem clock and the high-speed system
clock is stopped. For details, see CHAPTER 33 CAUTIONS FOR WAIT.
Be sure to clear bits 3 to 7 of ADS to 0.
If data is written to ADS, a wait cycle is generated. Do not write data to ADS
when the CPU is operating on the subsystem clock and the high-speed system
clock is stopped. For details, see CHAPTER 33 CAUTIONS FOR WAIT.
When writing to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR may become undefined. Read
the conversion result following conversion completion before writing to ADM and
ADS. Using timing other than the above may cause an incorrect conversion
result to be read.
If data is read from ADCR, a wait cycle is generated. Do not read data from
ADCR when the CPU is operating on the subsystem clock and the high-speed
system clock is stopped. For details, see CHAPTER 33 CAUTIONS FOR WAIT.
If data is written to PFM, a wait cycle is generated. Do not write data to PFM
when the CPU is operating on the subsystem clock and the high-speed system
clock is stopped. For details, see CHAPTER 33 CAUTIONS FOR WAIT.
If data is written to PFT, a wait cycle is generated. Do not write data to PFT when
the CPU is operating on the subsystem clock and the high-speed system clock is
stopped. For details, see CHAPTER 33 CAUTIONS FOR WAIT.
Make sure the period of <1> to <3> is 14 s or more.
It is no problem if the order of <1> and <2> is reversed.
<1> can be omitted. However, do not use the first conversion result after <3> in
this case.
The period from <4> to <7> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <6> to <7> is the conversion time set
using FR2 to FR0.
Make sure the period of <3> to <6> is 14 s or more.
It is no problem if order of <3>, <4>, and <5> is changed.
<3> must not be omitted if the power-fail function is used.
The period from <7> to <11> differs from the conversion time set using bits 5 to 3
(FR2 to FR0) of ADM. The period from <9> to <11> is the conversion time set
using FR2 to FR0.
The A/D converter stops operating in the standby mode. At this time, the
operating current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of
the A/D converter mode register (ADM) to 0 (see Figure 12-2).
Observe the rated range of the ANI0 to ANI7 input voltage. If a voltage of AV
or higher and AV
input to an analog input channel, the converted value of that channel becomes
undefined. In addition, the converted values of the other channels may also be
affected.
ADCR read has priority. After the read operation, the new conversion result is
written to ADCR.
ADM or ADS write has priority. ADCR write is not performed, nor is the
conversion end interrupt signal (INTAD) generated.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ3V0UD
SS
or lower (even in the range of absolute maximum ratings) is
Cautions
REF
p. 252
p. 253
p. 253
p. 254
p. 254
p. 255
p. 255
p. 261
p. 261
p. 261
p. 261
p. 261
p. 261
p. 261
p. 261
p. 264
p. 264
p. 264
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