UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 261

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.4.3 A/D converter operation mode
ANI7 by the analog input channel specification register (ADS) and A/D conversion is executed.
mode register (PFM).
(1) A/D conversion operation (when PFEN = 0)
The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to
In addition, the following two functions can be selected by setting of bit 7 (PFEN) of the power-fail comparison
A/D conversion
By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail
comparison mode register (PFM) to 0, the A/D conversion operation of the voltage, which is applied to the analog
input pin specified by the analog input channel specification register (ADS), is started.
When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result
register (ADCR), and an interrupt request signal (INTAD) is generated. Once the A/D conversion has started and
when one A/D conversion has been completed, the next A/D conversion operation is immediately started. The
A/D conversion operations are repeated until new data is written to ADS.
If ADM, ADS, the power-fail comparison mode register (PFM), and the power-fail comparison threshold register
(PFT) are rewritten during A/D conversion, the A/D conversion operation under execution is stopped and
restarted from the beginning.
If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped.
conversion result is undefined.
Remarks 1. n = 0 to 7
Normal 10-bit A/D converter (PFEN = 0)
Power-fail detection function (PFEN = 1)
(PFEN = 0)
INTAD
ADCR
2. m = 0 to 7
Rewriting ADM
ADCS = 1
ANIn
Figure 12-11. A/D Conversion Operation
CHAPTER 12 A/D CONVERTER
User’s Manual U16899EJ3V0UD
ANIn
ANIn
Conversion is stopped
Conversion result is not retained
Rewriting ADS
ANIn
ANIn
ANIm
ANIm
ADCS = 0
ANIm
At this time, the
Stopped
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