UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 237

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

10.3 Registers Controlling Watchdog Timer
(1) Watchdog timer mode register (WDTM)
Address: FF98H
The watchdog timer is controlled by the following two registers.
Symbol
WDTM
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
RESET input sets this register to 67H.
Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
Notes 1.
WDCS4
WDCS2
7
0
0
0
1
0
0
0
0
1
1
1
1
Note 1
Note 2
2.
After reset: 67H
WDCS3
WDCS1
If “internal oscillator cannot be stopped” is specified by the option byte, this cannot be set.
The internal oscillation clock will be selected no matter what value is written.
Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
Figure 10-2. Format of Watchdog Timer Mode Register (WDTM)
6
1
0
1
0
0
1
1
0
0
1
1
Note 1
Note 2
WDCS0
Internal oscillation clock (f
High-speed system clock (f
Watchdog timer operation stopped
R/W
0
1
0
1
0
1
0
1
5
1
CHAPTER 10 WATCHDOG TIMER
Note 2
User’s Manual U16899EJ3V0UD
During internal oscillation clock
2
2
2
2
2
2
2
2
11
12
13
14
15
16
17
18
WDCS4
/f
/f
/f
/f
/f
/f
/f
/f
R
R
R
R
R
R
R
R
4
(4.27 ms)
(8.53 ms)
(17.07 ms)
(34.13 ms)
(68.27 ms)
(136.53 ms)
(273.07 ms)
(546.13 ms)
operation
Operation clock selection
R
)
XP
WDCS3
)
3
Overflow time setting
WDCS2
2
During high-speed system clock
2
2
2
2
2
2
2
2
13
14
15
16
17
18
19
20
/f
/f
/f
/f
/f
/f
/f
/f
XP
XP
XP
XP
XP
XP
XP
XP
(819.2 s)
(1.64 ms)
(3.28 ms)
(6.55 ms)
(13.11 ms)
(26.21 ms)
(52.43 ms)
(104.86 ms)
WDCS1
operation
1
WDCS0
0
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