UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 430

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

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(2) Assemble in advance the initial setting routine as shown in Figure 25-6 to correct the program.
Note Whether the ROM correction is used or not should be judged by the port input level. For example, when the
(3) After reset, store the corrected address and program that have been previously stored in the external
(4) Set the main program so that the program branches from the specified address of the internal expansion RAM
(5) After the main program is started, the fetch address value and the values set in CORAD0 and CORAD1 are
(6) Branch to the address F7FDH by the correction branch request signal.
(7) Branch to the internal expansion RAM address set in (4) by the entire-space branch instruction of the address
(8) When one place is corrected, the correction program is executed. When two places are corrected, the
nonvolatile memory with initial setting routine for ROM correction of the user to internal expansion RAM (see
Figure 25-6).
Set the start address of the instruction to be corrected to CORAD0 and CORAD1, and set bits 1 and 3
(COREN0, COREN1) of the correction control register (CORCN) to 1.
(F7FDH) to the internal expansion RAM address where the corrected program is stored using the entire space
branch instruction (BR !addr16).
always compared by the comparator in the ROM correction circuit. When these values match, the correction
branch request signal is generated. Simultaneously the corresponding correction status flag (CORST0 or
CORST1) is set to 1.
F7FDH.
correction status flag is checked with the branch destination judgment program, and branches to the correction
program.
P20 input level is high, the ROM correction is used, otherwise, it is not used.
Load the contents of external nonvolatile memory
into internal expansion RAM
Correction address register setting
ROM correction operation enabled
correction used ?
Figure 25-6. Initial Setting Routine
Main program
Initial setting
CHAPTER 25 ROM CORRECTION
Is ROM
User’s Manual U16899EJ3V0UD
Yes
Note
No
ROM correction