UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 239

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Internal
Reset Signal
Generation Cause
Watchdog timer
overflows
Write to WDTM for the
second time
Write other than “ACH”
to WDTE
Access WDTE by 1-bit
memory manipulation
instruction
The relationship between the watchdog timer operation and the internal reset signal generated by the watchdog
timer is shown below.
Watchdog Timer
Operation
Table 10-4. Relationship Between Watchdog Timer Operation and
Selected by Option Byte
Internal reset signal is
generated.
Internal reset signal is
generated.
Internal reset signal is
generated.
Cannot Be Stopped ” Is
(Watchdog Timer Is
Always Operating)
“Internal Oscillator
Internal Reset Signal Generated by Watchdog Timer
CHAPTER 10 WATCHDOG TIMER
User’s Manual U16899EJ3V0UD
Internal reset signal is
generated.
Internal reset signal is
generated.
Internal reset signal is
generated.
“Internal Oscillator Can Be Stopped by Software” Is Selected by Option Byte
Watchdog Timer Is
Operating
Internal reset signal is
not generated and the
watchdog timer does
not resume operation.
Internal reset signal is
not generated.
WDCS4 Is Set to 1
Watchdog Timer Stopped
Internal reset signal is
generated when the
source clock to the
watchdog timer
resumes operation.
Internal reset signal is
generated when the
source clock to the
watchdog timer
resumes operation.
Watchdog Timer Is
Source Clock to
Stopped
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