UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 471

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UPD78F0138HGK-9ET-A

Manufacturer Part Number
UPD78F0138HGK-9ET-A
Description
MCU 8BIT 60K FLASH 64TQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx1+r
Datasheet

Specifications of UPD78F0138HGK-9ET-A

Core Processor
78K/0
Core Size
8-Bit
Speed
16MHz
Connectivity
3-Wire SIO, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
42
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
8-bit
operation
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
3.
SUB
SUBC
AND
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
Except “r = A”
control register (PCC).
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
A, #byte
saddr, #byte
A, r
r, A
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, [HL + B]
A, [HL + C]
Operands
CHAPTER 28 INSTRUCTION SET
Note 3
Note 3
Note 3
User’s Manual U16899EJ3V0UD
Bytes
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
2
3
2
2
2
3
1
2
2
2
Note 1
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
4
6
4
4
4
8
4
8
8
8
Clocks
Note 2
8
8
8
5
9
5
9
9
9
5
9
5
9
9
9
5
9
5
9
9
9
A, CY
(saddr), CY
A, CY
r, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
(saddr), CY
A, CY
r, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A, CY
A
(saddr)
A
r
A
A
A
A
A
A
r
A
A
A
A
A
A
A
A
A
r
r
byte
r
(saddr)
(addr16)
[HL]
[HL + byte]
[HL + B]
[HL + C]
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
(saddr)
A
A
CPU
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
(HL + B)
(HL + C)
byte
r
(saddr)
(addr16)
(HL)
(HL + byte)
(HL + B)
(HL + C)
(saddr)
(saddr)
CY
) selected by the processor clock
CY
Operation
CY
CY
byte
CY
CY
CY
CY
byte
byte
CY
CY
Z AC CY
Flag
469

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