UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 258

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UPD78F0138HGK-9ET-A

Manufacturer Part Number
UPD78F0138HGK-9ET-A
Description
MCU 8BIT 60K FLASH 64TQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx1+r
Datasheet

Specifications of UPD78F0138HGK-9ET-A

Core Processor
78K/0
Core Size
8-Bit
Speed
16MHz
Connectivity
3-Wire SIO, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
42
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
12.4 A/D Converter Operations
12.4.1 Basic operations of A/D converter
256
<1> Select one channel for A/D conversion using the analog input channel specification register (ADS).
<2> Set ADCE to 1 and wait for 14 s or longer.
<3> Set ADCS to 1 and start the conversion operation.
<4> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<5> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
<6> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to
<7> The voltage difference between the series resistor string voltage tap and analog input is compared by the
<8> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series
<9> Comparison is continued in this way up to bit 0 of SAR.
<10> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result
<11> Repeat steps <4> to <10>, until ADCS is cleared to 0.
(<4> to <10> are operations performed by hardware.)
input analog voltage is held until the A/D conversion operation has ended.
(1/2) AV
voltage comparator. If the analog input is greater than (1/2) AV
analog input is smaller than (1/2) AV
resistor string voltage tap is selected according to the preset value of bit 9, as described below.
The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows.
value is transferred to the A/D conversion result register (ADCR) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the
status of ADCE = 0, however, start from <2>.
Bit 9 = 1: (3/4) AV
Bit 9 = 0: (1/4) AV
Analog input voltage
Analog input voltage < Voltage tap: Bit 8 = 0
REF
by the tap selector.
REF
REF
Voltage tap: Bit 8 = 1
CHAPTER 12 A/D CONVERTER
REF
User’s Manual U16899EJ3V0UD
, the MSB is reset to 0.
REF
, the MSB of SAR remains set to 1. If the

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