UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 543

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16-bit
timer/
event
counters
00, 01
(TM00,
TM01)
Function
CR00n: 16-bit
timer
capture/compar
e register 00n
CR01n: 16-bit
timer
capture/compar
e register 01n
TMC0n: 16-bit
timer mode
control register
0n
TMC00: 16-bit
timer mode
control register
00
TMC01: 16-bit
timer mode
control register
01
Details of
Function
Set a value other than 0000H in CR00n in the mode in which clear & start occurs
on a match of TM0n and CR00n.
If CR00n is cleared to 0000H in the free-running mode and in the clear mode
using the valid edge of the TI00n pin, an interrupt request (INTTM00n) is
generated when the value of CR00n changes from 0000H to 0001H following
TM0n overflow (FFFFH). In addition, INTTM00n is generated after a match
between TM0n and CR00n, after detecting the valid edge of the TI01n pin, or
the timer is cleared by a one-shot trigger.
When the valid edge of the TI01n pin is used, P01 or P06 cannot be used as the
timer output pin (TO0n). When P01 or P06 is used as the TO0n pin, the valid
edge of the TI01n pin cannot be used.
When CR00n is used as a capture register, read data is undefined if the register
read time and capture trigger input conflict (the capture data itself is the correct
value). If a timer count stop and a capture trigger input conflict, the captured data
is undefined.
Do not rewrite CR00n during TM0n operation.
If the CR01n register is cleared to 0000H, an interrupt request (INTTM01n) is
generated when the value of CR01n changes from 0000H to 0001H following
TM0n overflow (FFFFH). In addition, INTTM01n is generated after a match
between TM0n and CR01n, after detecting the valid edge of the TI00n pin, or the
timer is cleared by a one-shot trigger.
When CR01n is used as a capture register, read data is undefined if the register
read time and capture trigger input conflict (the capture data itself is the correct
value).
If count stop input and capture trigger input conflict, the captured data is
undefined.
CR01n can be rewritten during TM0n operation. For details, see Caution 2 in
Figure 6-20.
16-bit timer counter 0n (TM0n) starts operation at the moment TMC0n2 and
TMC0n3 are set to values other than 0, 0 (operation stop mode), respectively. Set
TMC0n2 and TMC0n3 to 0, 0 to stop the operation.
Timer operation must be stopped before writing to bits other than the OVF00 flag. p. 144
Set the valid edge of the TI000/P00 pin using prescaler mode register 00
(PRM00).
If the following modes: the mode in which clear & start occurs on match between
TM00 and CR000, the mode in which clear & start occurs at the TI000 pin valid
edge, or free-running mode is selected, when the set value of CR000 is FFFFH
and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1.
Timer operation must be stopped before writing to bits other than the OVF01 flag. p. 145
Set the valid edge of the TI001/P05 pin using prescaler mode register
01(PRM01).
If the following modes: the mode in which clear & start occurs on match between
TM01 and CR001, the mode in which clear & start occurs at the TI001 pin valid
edge, or free-running mode is selected, when the set value of CR001 is FFFFH
and the TM01 value changes from FFFFH to 0000H, the OVF01 flag is set to 1.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16899EJ3V0UD
Cautions
p. 141
p. 141
p. 141
p. 141
pp. 141,
154,
159,
171
p. 142
p. 142
p. 142
p. 143
p. 144
p. 144
p. 145
p. 145
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