UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 243

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

(3) When the CPU clock is the internal oscillation clock (f
Note Confirm the oscillation stabilization time of f
CPU operation
high-speed system clock (f
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started
using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds
its value.
<1> The oscillation stabilization time set by the oscillation stabilization time select register (OSTS) elapses.
<2> The CPU clock is switched to the high-speed system clock (f
<1> Timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time
<2> Timing when counting is started after the CPU clock is switched to the high-speed system clock (f
CPU operation
Watchdog timer
Watchdog timer
(OSTC).
select register (OSTS) has elapsed
(CPU Clock: Internal Oscillator Clock, WDT Operation Clock: High-Speed System Clock)
f
f
XP
f
XP
f
R
R
Normal operation
Normal operation
(internal
(internal
oscillation clock)
oscillation clock)
Operating
Operating
XP
) when the STOP instruction is executed
Oscillation
Oscillation
stopped
stopped
Figure 10-6. Operation in STOP Mode
STOP
STOP
CHAPTER 10 WATCHDOG TIMER
(internal oscillation clock)
User’s Manual U16899EJ3V0UD
Operation stopped
Operation stopped
Oscillation stabilization time
Clock supply stopped
Normal operation
Oscillation stabilization time
(set by OSTS register)
Clock supply
XP
17 clocks
(set by OSTS register)
17 clocks
stopped
using the oscillation stabilization time counter status register
R
) and the watchdog timer operation clock is the
XP
).
Normal operation (internal oscillation clock)
CPU clock
f
R
Normal operation (high-speed system clock)
f
XP
Note
Operating
Operating
XP
)
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