UPD78F0138HGK-9ET-A Renesas Electronics America, UPD78F0138HGK-9ET-A Datasheet - Page 354

• Manufacturer Part Number: UPD78F0138HGK-9ET-A
• Description: MCU 8BIT 60K FLASH 64TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx1+r

Specifications of UPD78F0138HGK-9ET-A

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: 3-Wire SIO, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 42
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.3 Register Controlling Multiplier/Divider
352
Address: FF68H
The multiplier/divider is controlled by multiplier/divider control register 0 (DMUC0).
DMUC0
Symbol
(1) Multiplier/divider control register 0 (DMUC0)
Note When DMUE is set to 1, the operation is started. DMUE is automatically cleared to 0 after the operation is
Cautions 1. If DMUE is cleared to 0 during operation processing (when DMUE is 1), the operation result
DMUC0 is an 8-bit register that controls the operation of the multiplier/divider.
This register can be read by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears this register to 00H.
complete.
2. Do not change the value of DMUSEL0 during operation processing (while DMUE is 1). If it is
3. If DMUE is cleared to 0 during operation processing (while DMUE is 1), the operation
DMUSEL0
DMUE
DMUE
After reset: 00H
<7>
is not guaranteed. If the operation is completed while the clearing instruction is being
executed, the operation result is guaranteed, provided that the interrupt flag is set.
changed, undefined operation results are stored in multiplication/division data register A0
(MDA0) and remainder data register 0 (SDR0).
processing is stopped. To execute the operation again, set multiplication/division data
register A0 (MDA0), multiplication/division data register B0 (MDB0), and multiplier/divider
control register 0 (DMUC0), and start the operation (by clearing DMUE to 1).
0
1
0
1
Figure 16-5. Format of Multiplier/Divider Control Register 0 (DMUC0)
Note
Stops operation
Starts operation
Division mode
Multiplication mode
6
0
R/W
CHAPTER 16 MULTIPLIER/DIVIDER
5
0
User’s Manual U16899EJ3V0UD
Operation mode (multiplication/division) selection
4
0
Operation start/stop
3
0
2
0
1
0
DMUSEL0
0